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idpf: refactor idpf to use libie control queues

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Support to initialize and configure controlqs, and manage their
transactions was introduced in libie. As part of it, most of the existing
controlq structures are renamed and modified. Use those APIs in idpf and
make all the necessary changes.

Previously for the send and receive virtchnl messages, there used to be a
memcpy involved in controlq code to copy the buffer info passed by the send
function into the controlq specific buffers. There was no restriction to
use automatic memory in that case. The new implementation in libie removed
copying of the send buffer info and introduced DMA mapping of the send
buffer itself. To accommodate it, use dynamic memory for the larger send
buffers. For smaller ones (<= 128 bytes) libie still can copy them into the
pre-allocated message memory. Those changes result in a pretty big diff,
but the changes are fairly trivial and localized.

In case of receive, idpf receives a page pool buffer allocated by the libie
and care should be taken to release it after use in the idpf.

idpf_idc_rdma_vc_send_sync() no longer truncates oversized responses or
zeroes *recv_len on error, but this was confirmed to have no practical
impact for any existing callers.

This refactoring introduces roughly additional 40KB of module storage used
for systems that only run idpf, so idpf + libie_cp + libie_pci takes about
7% more storage than just idpf before refactoring.

We now pre-allocate small TX buffers, so that does increase the memory
usage, but reduces the need to allocate. This results in additional 256 *
128B of memory permanently used, increasing the worst-case memory usage by
32KB but our ctlq RX buffers need to be of size 4096B anyway (not changed
by the patchset), so this is hardly noticeable.

As for the timings, the fact that we are mostly limited by the HW response
time which is far from instant, is not changed by this refactor.

Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Signed-off-by: Pavan Kumar Linga <pavan.kumar.linga@intel.com>
Tested-by: Samuel Salin <Samuel.salin@intel.com>
Co-developed-by: Larysa Zaremba <larysa.zaremba@intel.com>
Signed-off-by: Larysa Zaremba <larysa.zaremba@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
This commit is contained in:
Pavan Kumar Linga 2026-06-25 18:02:03 +02:00 committed by Tony Nguyen
parent 6b284aa2dd
commit deaada4f18
16 changed files with 859 additions and 2499 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/ethernet/intel/idpf/Makefile
View File

@ -6,8 +6,6 @@
obj-$(CONFIG_IDPF) += idpf.o
idpf-y := \
idpf_controlq.o \
idpf_controlq_setup.o \
idpf_dev.o \
idpf_ethtool.o \
idpf_idc.o \

28
drivers/net/ethernet/intel/idpf/idpf.h
View File

@ -27,7 +27,6 @@ struct idpf_rss_data;
#include <linux/net/intel/virtchnl2.h>
#include "idpf_txrx.h"
#include "idpf_controlq.h"
#define GETMAXVAL(num_bits) GENMASK((num_bits) - 1, 0)
@ -37,11 +36,10 @@ struct idpf_rss_data;
#define IDPF_NUM_FILTERS_PER_MSG 20
#define IDPF_NUM_DFLT_MBX_Q 2 /* includes both TX and RX */
#define IDPF_DFLT_MBX_Q_LEN 64
#define IDPF_DFLT_MBX_ID -1
/* maximum number of times to try before resetting mailbox */
#define IDPF_MB_MAX_ERR 20
#define IDPF_NUM_CHUNKS_PER_MSG(struct_sz, chunk_sz) \
((IDPF_CTLQ_MAX_BUF_LEN - (struct_sz)) / (chunk_sz))
((LIBIE_CTLQ_MAX_BUF_LEN - (struct_sz)) / (chunk_sz))
#define IDPF_WAIT_FOR_MARKER_TIMEO 500
#define IDPF_MAX_WAIT 500
@ -202,8 +200,8 @@ struct idpf_vport_max_q {
* @ptp_reg_init: PTP register initialization
*/
struct idpf_reg_ops {
void (*ctlq_reg_init)(struct idpf_adapter *adapter,
struct idpf_ctlq_create_info *cq);
void (*ctlq_reg_init)(struct libie_mmio_info *mmio,
struct libie_ctlq_create_info *cctlq_info);
int (*intr_reg_init)(struct idpf_vport *vport,
struct idpf_q_vec_rsrc *rsrc);
void (*mb_intr_reg_init)(struct idpf_adapter *adapter);
@ -606,8 +604,6 @@ struct idpf_vport_config {
DECLARE_BITMAP(flags, IDPF_VPORT_CONFIG_FLAGS_NBITS);
};
struct idpf_vc_xn_manager;
#define idpf_for_each_vport(adapter, iter) \
for (struct idpf_vport **__##iter = &(adapter)->vports[0], \
*iter = (adapter)->max_vports ? *__##iter : NULL; \
@ -625,8 +621,10 @@ struct idpf_vc_xn_manager;
* @state: Init state machine
* @flags: See enum idpf_flags
* @reset_reg: See struct idpf_reset_reg
* @hw: Device access data
* @ctlq_ctx: controlq context
* @asq: Send control queue info
* @arq: Receive control queue info
* @xnm: Xn transaction manager
* @num_avail_msix: Available number of MSIX vectors
* @num_msix_entries: Number of entries in MSIX table
* @msix_entries: MSIX table
@ -659,7 +657,6 @@ struct idpf_vc_xn_manager;
* @stats_task: Periodic statistics retrieval task
* @stats_wq: Workqueue for statistics task
* @caps: Negotiated capabilities with device
* @vcxn_mngr: Virtchnl transaction manager
* @dev_ops: See idpf_dev_ops
* @cdev_info: IDC core device info pointer
* @num_vfs: Number of allocated VFs through sysfs. PF does not directly talk
@ -683,8 +680,10 @@ struct idpf_adapter {
enum idpf_state state;
DECLARE_BITMAP(flags, IDPF_FLAGS_NBITS);
struct idpf_reset_reg reset_reg;
struct idpf_hw hw;
struct libie_ctlq_ctx ctlq_ctx;
struct libie_ctlq_info *asq;
struct libie_ctlq_info *arq;
struct libie_ctlq_xn_manager *xnm;
u16 num_avail_msix;
u16 num_msix_entries;
struct msix_entry *msix_entries;
@ -721,7 +720,6 @@ struct idpf_adapter {
struct delayed_work stats_task;
struct workqueue_struct *stats_wq;
struct virtchnl2_get_capabilities caps;
struct idpf_vc_xn_manager *vcxn_mngr;
struct idpf_dev_ops dev_ops;
struct iidc_rdma_core_dev_info *cdev_info;
@ -881,12 +879,12 @@ static inline u8 idpf_get_min_tx_pkt_len(struct idpf_adapter *adapter)
*/
static inline bool idpf_is_reset_detected(struct idpf_adapter *adapter)
{
if (!adapter->hw.arq)
struct libie_ctlq_info *arq = adapter->arq;
if (!arq)
return true;
return !(readl(libie_pci_get_mmio_addr(&adapter->ctlq_ctx.mmio_info,
adapter->hw.arq->reg.len)) &
adapter->hw.arq->reg.len_mask);
return !(readl(arq->reg.len) & arq->reg.len_mask);
}
/**

631
drivers/net/ethernet/intel/idpf/idpf_controlq.c
View File

@ -1,631 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (C) 2023 Intel Corporation */
#include "idpf.h"
/**
* idpf_ctlq_setup_regs - initialize control queue registers
* @cq: pointer to the specific control queue
* @q_create_info: structs containing info for each queue to be initialized
*/
static void idpf_ctlq_setup_regs(struct idpf_ctlq_info *cq,
struct idpf_ctlq_create_info *q_create_info)
{
/* set control queue registers in our local struct */
cq->reg.head = q_create_info->reg.head;
cq->reg.tail = q_create_info->reg.tail;
cq->reg.len = q_create_info->reg.len;
cq->reg.bah = q_create_info->reg.bah;
cq->reg.bal = q_create_info->reg.bal;
cq->reg.len_mask = q_create_info->reg.len_mask;
cq->reg.len_ena_mask = q_create_info->reg.len_ena_mask;
cq->reg.head_mask = q_create_info->reg.head_mask;
}
/**
* idpf_ctlq_init_regs - Initialize control queue registers
* @hw: pointer to hw struct
* @cq: pointer to the specific Control queue
* @is_rxq: true if receive control queue, false otherwise
*
* Initialize registers. The caller is expected to have already initialized the
* descriptor ring memory and buffer memory
*/
static void idpf_ctlq_init_regs(struct idpf_hw *hw, struct idpf_ctlq_info *cq,
bool is_rxq)
{
struct libie_mmio_info *mmio = &hw->back->ctlq_ctx.mmio_info;
/* Update tail to post pre-allocated buffers for rx queues */
if (is_rxq)
writel((u32)(cq->ring_size - 1),
libie_pci_get_mmio_addr(mmio, cq->reg.tail));
/* For non-Mailbox control queues only TAIL need to be set */
if (cq->q_id != -1)
return;
/* Clear Head for both send or receive */
writel(0, libie_pci_get_mmio_addr(mmio, cq->reg.head));
/* set starting point */
writel(lower_32_bits(cq->desc_ring.pa),
libie_pci_get_mmio_addr(mmio, cq->reg.bal));
writel(upper_32_bits(cq->desc_ring.pa),
libie_pci_get_mmio_addr(mmio, cq->reg.bah));
writel((cq->ring_size | cq->reg.len_ena_mask),
libie_pci_get_mmio_addr(mmio, cq->reg.len));
}
/**
* idpf_ctlq_init_rxq_bufs - populate receive queue descriptors with buf
* @cq: pointer to the specific Control queue
*
* Record the address of the receive queue DMA buffers in the descriptors.
* The buffers must have been previously allocated.
*/
static void idpf_ctlq_init_rxq_bufs(struct idpf_ctlq_info *cq)
{
int i;
for (i = 0; i < cq->ring_size; i++) {
struct idpf_ctlq_desc *desc = IDPF_CTLQ_DESC(cq, i);
struct idpf_dma_mem *bi = cq->bi.rx_buff[i];
/* No buffer to post to descriptor, continue */
if (!bi)
continue;
desc->flags =
cpu_to_le16(IDPF_CTLQ_FLAG_BUF | IDPF_CTLQ_FLAG_RD);
desc->opcode = 0;
desc->datalen = cpu_to_le16(bi->size);
desc->ret_val = 0;
desc->v_opcode_dtype = 0;
desc->v_retval = 0;
desc->params.indirect.addr_high =
cpu_to_le32(upper_32_bits(bi->pa));
desc->params.indirect.addr_low =
cpu_to_le32(lower_32_bits(bi->pa));
desc->params.indirect.param0 = 0;
desc->params.indirect.sw_cookie = 0;
desc->params.indirect.v_flags = 0;
}
}
/**
* idpf_ctlq_shutdown - shutdown the CQ
* @hw: pointer to hw struct
* @cq: pointer to the specific Control queue
*
* The main shutdown routine for any controq queue
*/
static void idpf_ctlq_shutdown(struct idpf_hw *hw, struct idpf_ctlq_info *cq)
{
spin_lock(&cq->cq_lock);
/* free ring buffers and the ring itself */
idpf_ctlq_dealloc_ring_res(hw, cq);
/* Set ring_size to 0 to indicate uninitialized queue */
cq->ring_size = 0;
spin_unlock(&cq->cq_lock);
}
/**
* idpf_ctlq_add - add one control queue
* @hw: pointer to hardware struct
* @qinfo: info for queue to be created
* @cq_out: (output) double pointer to control queue to be created
*
* Allocate and initialize a control queue and add it to the control queue list.
* The cq parameter will be allocated/initialized and passed back to the caller
* if no errors occur.
*
* Note: idpf_ctlq_init must be called prior to any calls to idpf_ctlq_add
*/
int idpf_ctlq_add(struct idpf_hw *hw,
struct idpf_ctlq_create_info *qinfo,
struct idpf_ctlq_info **cq_out)
{
struct idpf_ctlq_info *cq;
bool is_rxq = false;
int err;
cq = kzalloc_obj(*cq);
if (!cq)
return -ENOMEM;
cq->cq_type = qinfo->type;
cq->q_id = qinfo->id;
cq->buf_size = qinfo->buf_size;
cq->ring_size = qinfo->len;
cq->next_to_use = 0;
cq->next_to_clean = 0;
cq->next_to_post = cq->ring_size - 1;
switch (qinfo->type) {
case IDPF_CTLQ_TYPE_MAILBOX_RX:
is_rxq = true;
fallthrough;
case IDPF_CTLQ_TYPE_MAILBOX_TX:
err = idpf_ctlq_alloc_ring_res(hw, cq);
break;
default:
err = -EBADR;
break;
}
if (err)
goto init_free_q;
if (is_rxq) {
idpf_ctlq_init_rxq_bufs(cq);
} else {
/* Allocate the array of msg pointers for TX queues */
cq->bi.tx_msg = kzalloc_objs(struct idpf_ctlq_msg *, qinfo->len);
if (!cq->bi.tx_msg) {
err = -ENOMEM;
goto init_dealloc_q_mem;
}
}
idpf_ctlq_setup_regs(cq, qinfo);
idpf_ctlq_init_regs(hw, cq, is_rxq);
spin_lock_init(&cq->cq_lock);
list_add(&cq->cq_list, &hw->cq_list_head);
*cq_out = cq;
return 0;
init_dealloc_q_mem:
/* free ring buffers and the ring itself */
idpf_ctlq_dealloc_ring_res(hw, cq);
init_free_q:
kfree(cq);
return err;
}
/**
* idpf_ctlq_remove - deallocate and remove specified control queue
* @hw: pointer to hardware struct
* @cq: pointer to control queue to be removed
*/
void idpf_ctlq_remove(struct idpf_hw *hw,
struct idpf_ctlq_info *cq)
{
list_del(&cq->cq_list);
idpf_ctlq_shutdown(hw, cq);
kfree(cq);
}
/**
* idpf_ctlq_init - main initialization routine for all control queues
* @hw: pointer to hardware struct
* @num_q: number of queues to initialize
* @q_info: array of structs containing info for each queue to be initialized
*
* This initializes any number and any type of control queues. This is an all
* or nothing routine; if one fails, all previously allocated queues will be
* destroyed. This must be called prior to using the individual add/remove
* APIs.
*/
int idpf_ctlq_init(struct idpf_hw *hw, u8 num_q,
struct idpf_ctlq_create_info *q_info)
{
struct idpf_ctlq_info *cq, *tmp;
int err;
int i;
INIT_LIST_HEAD(&hw->cq_list_head);
for (i = 0; i < num_q; i++) {
struct idpf_ctlq_create_info *qinfo = q_info + i;
err = idpf_ctlq_add(hw, qinfo, &cq);
if (err)
goto init_destroy_qs;
}
return 0;
init_destroy_qs:
list_for_each_entry_safe(cq, tmp, &hw->cq_list_head, cq_list)
idpf_ctlq_remove(hw, cq);
return err;
}
/**
* idpf_ctlq_deinit - destroy all control queues
* @hw: pointer to hw struct
*/
void idpf_ctlq_deinit(struct idpf_hw *hw)
{
struct idpf_ctlq_info *cq, *tmp;
list_for_each_entry_safe(cq, tmp, &hw->cq_list_head, cq_list)
idpf_ctlq_remove(hw, cq);
}
/**
* idpf_ctlq_send - send command to Control Queue (CTQ)
* @hw: pointer to hw struct
* @cq: handle to control queue struct to send on
* @num_q_msg: number of messages to send on control queue
* @q_msg: pointer to array of queue messages to be sent
*
* The caller is expected to allocate DMAable buffers and pass them to the
* send routine via the q_msg struct / control queue specific data struct.
* The control queue will hold a reference to each send message until
* the completion for that message has been cleaned.
*/
int idpf_ctlq_send(struct idpf_hw *hw, struct idpf_ctlq_info *cq,
u16 num_q_msg, struct idpf_ctlq_msg q_msg[])
{
struct idpf_ctlq_desc *desc;
int num_desc_avail;
int err = 0;
int i;
spin_lock(&cq->cq_lock);
/* Ensure there are enough descriptors to send all messages */
num_desc_avail = IDPF_CTLQ_DESC_UNUSED(cq);
if (num_desc_avail == 0 || num_desc_avail < num_q_msg) {
err = -ENOSPC;
goto err_unlock;
}
for (i = 0; i < num_q_msg; i++) {
struct idpf_ctlq_msg *msg = &q_msg[i];
desc = IDPF_CTLQ_DESC(cq, cq->next_to_use);
desc->opcode = cpu_to_le16(msg->opcode);
desc->pfid_vfid = cpu_to_le16(msg->func_id);
desc->v_opcode_dtype = cpu_to_le32(msg->cookie.mbx.chnl_opcode);
desc->v_retval = cpu_to_le32(msg->cookie.mbx.chnl_retval);
desc->flags = cpu_to_le16((msg->host_id & IDPF_HOST_ID_MASK) <<
IDPF_CTLQ_FLAG_HOST_ID_S);
if (msg->data_len) {
struct idpf_dma_mem *buff = msg->ctx.indirect.payload;
desc->datalen |= cpu_to_le16(msg->data_len);
desc->flags |= cpu_to_le16(IDPF_CTLQ_FLAG_BUF);
desc->flags |= cpu_to_le16(IDPF_CTLQ_FLAG_RD);
/* Update the address values in the desc with the pa
* value for respective buffer
*/
desc->params.indirect.addr_high =
cpu_to_le32(upper_32_bits(buff->pa));
desc->params.indirect.addr_low =
cpu_to_le32(lower_32_bits(buff->pa));
memcpy(&desc->params, msg->ctx.indirect.context,
IDPF_INDIRECT_CTX_SIZE);
} else {
memcpy(&desc->params, msg->ctx.direct,
IDPF_DIRECT_CTX_SIZE);
}
/* Store buffer info */
cq->bi.tx_msg[cq->next_to_use] = msg;
(cq->next_to_use)++;
if (cq->next_to_use == cq->ring_size)
cq->next_to_use = 0;
}
/* Force memory write to complete before letting hardware
* know that there are new descriptors to fetch.
*/
dma_wmb();
writel(cq->next_to_use,
libie_pci_get_mmio_addr(&hw->back->ctlq_ctx.mmio_info,
cq->reg.tail));
err_unlock:
spin_unlock(&cq->cq_lock);
return err;
}
/**
* idpf_ctlq_clean_sq - reclaim send descriptors on HW write back for the
* requested queue
* @cq: pointer to the specific Control queue
* @clean_count: (input|output) number of descriptors to clean as input, and
* number of descriptors actually cleaned as output
* @msg_status: (output) pointer to msg pointer array to be populated; needs
* to be allocated by caller
*
* Returns an array of message pointers associated with the cleaned
* descriptors. The pointers are to the original ctlq_msgs sent on the cleaned
* descriptors. The status will be returned for each; any messages that failed
* to send will have a non-zero status. The caller is expected to free original
* ctlq_msgs and free or reuse the DMA buffers.
*/
int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count,
struct idpf_ctlq_msg *msg_status[])
{
struct idpf_ctlq_desc *desc;
u16 i, num_to_clean;
u16 ntc, desc_err;
if (*clean_count == 0)
return 0;
if (*clean_count > cq->ring_size)
return -EBADR;
spin_lock(&cq->cq_lock);
ntc = cq->next_to_clean;
num_to_clean = *clean_count;
for (i = 0; i < num_to_clean; i++) {
/* Fetch next descriptor and check if marked as done */
desc = IDPF_CTLQ_DESC(cq, ntc);
if (!(le16_to_cpu(desc->flags) & IDPF_CTLQ_FLAG_DD))
break;
/* Ensure no other fields are read until DD flag is checked */
dma_rmb();
/* strip off FW internal code */
desc_err = le16_to_cpu(desc->ret_val) & 0xff;
msg_status[i] = cq->bi.tx_msg[ntc];
msg_status[i]->status = desc_err;
cq->bi.tx_msg[ntc] = NULL;
/* Zero out any stale data */
memset(desc, 0, sizeof(*desc));
ntc++;
if (ntc == cq->ring_size)
ntc = 0;
}
cq->next_to_clean = ntc;
spin_unlock(&cq->cq_lock);
/* Return number of descriptors actually cleaned */
*clean_count = i;
return 0;
}
/**
* idpf_ctlq_post_rx_buffs - post buffers to descriptor ring
* @hw: pointer to hw struct
* @cq: pointer to control queue handle
* @buff_count: (input|output) input is number of buffers caller is trying to
* return; output is number of buffers that were not posted
* @buffs: array of pointers to dma mem structs to be given to hardware
*
* Caller uses this function to return DMA buffers to the descriptor ring after
* consuming them; buff_count will be the number of buffers.
*
* Note: this function needs to be called after a receive call even
* if there are no DMA buffers to be returned, i.e. buff_count = 0,
* buffs = NULL to support direct commands
*/
int idpf_ctlq_post_rx_buffs(struct idpf_hw *hw, struct idpf_ctlq_info *cq,
u16 *buff_count, struct idpf_dma_mem **buffs)
{
struct idpf_ctlq_desc *desc;
u16 ntp = cq->next_to_post;
bool buffs_avail = false;
u16 tbp = ntp + 1;
int i = 0;
if (*buff_count > cq->ring_size)
return -EBADR;
if (*buff_count > 0)
buffs_avail = true;
spin_lock(&cq->cq_lock);
if (tbp >= cq->ring_size)
tbp = 0;
if (tbp == cq->next_to_clean)
/* Nothing to do */
goto post_buffs_out;
/* Post buffers for as many as provided or up until the last one used */
while (ntp != cq->next_to_clean) {
desc = IDPF_CTLQ_DESC(cq, ntp);
if (cq->bi.rx_buff[ntp])
goto fill_desc;
if (!buffs_avail) {
/* If the caller hasn't given us any buffers or
* there are none left, search the ring itself
* for an available buffer to move to this
* entry starting at the next entry in the ring
*/
tbp = ntp + 1;
/* Wrap ring if necessary */
if (tbp >= cq->ring_size)
tbp = 0;
while (tbp != cq->next_to_clean) {
if (cq->bi.rx_buff[tbp]) {
cq->bi.rx_buff[ntp] =
cq->bi.rx_buff[tbp];
cq->bi.rx_buff[tbp] = NULL;
/* Found a buffer, no need to
* search anymore
*/
break;
}
/* Wrap ring if necessary */
tbp++;
if (tbp >= cq->ring_size)
tbp = 0;
}
if (tbp == cq->next_to_clean)
goto post_buffs_out;
} else {
/* Give back pointer to DMA buffer */
cq->bi.rx_buff[ntp] = buffs[i];
i++;
if (i >= *buff_count)
buffs_avail = false;
}
fill_desc:
desc->flags =
cpu_to_le16(IDPF_CTLQ_FLAG_BUF | IDPF_CTLQ_FLAG_RD);
/* Post buffers to descriptor */
desc->datalen = cpu_to_le16(cq->bi.rx_buff[ntp]->size);
desc->params.indirect.addr_high =
cpu_to_le32(upper_32_bits(cq->bi.rx_buff[ntp]->pa));
desc->params.indirect.addr_low =
cpu_to_le32(lower_32_bits(cq->bi.rx_buff[ntp]->pa));
ntp++;
if (ntp == cq->ring_size)
ntp = 0;
}
post_buffs_out:
/* Only update tail if buffers were actually posted */
if (cq->next_to_post != ntp) {
if (ntp)
/* Update next_to_post to ntp - 1 since current ntp
* will not have a buffer
*/
cq->next_to_post = ntp - 1;
else
/* Wrap to end of end ring since current ntp is 0 */
cq->next_to_post = cq->ring_size - 1;
dma_wmb();
writel(cq->next_to_post,
libie_pci_get_mmio_addr(&hw->back->ctlq_ctx.mmio_info,
cq->reg.tail));
}
spin_unlock(&cq->cq_lock);
/* return the number of buffers that were not posted */
*buff_count = *buff_count - i;
return 0;
}
/**
* idpf_ctlq_recv - receive control queue message call back
* @cq: pointer to control queue handle to receive on
* @num_q_msg: (input|output) input number of messages that should be received;
* output number of messages actually received
* @q_msg: (output) array of received control queue messages on this q;
* needs to be pre-allocated by caller for as many messages as requested
*
* Called by interrupt handler or polling mechanism. Caller is expected
* to free buffers
*/
int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg,
struct idpf_ctlq_msg *q_msg)
{
u16 num_to_clean, ntc, flags;
struct idpf_ctlq_desc *desc;
int err = 0;
u16 i;
/* take the lock before we start messing with the ring */
spin_lock(&cq->cq_lock);
ntc = cq->next_to_clean;
num_to_clean = *num_q_msg;
for (i = 0; i < num_to_clean; i++) {
/* Fetch next descriptor and check if marked as done */
desc = IDPF_CTLQ_DESC(cq, ntc);
flags = le16_to_cpu(desc->flags);
if (!(flags & IDPF_CTLQ_FLAG_DD))
break;
/* Ensure no other fields are read until DD flag is checked */
dma_rmb();
q_msg[i].vmvf_type = (flags &
(IDPF_CTLQ_FLAG_FTYPE_VM |
IDPF_CTLQ_FLAG_FTYPE_PF)) >>
IDPF_CTLQ_FLAG_FTYPE_S;
if (flags & IDPF_CTLQ_FLAG_ERR)
err = -EBADMSG;
q_msg[i].cookie.mbx.chnl_opcode =
le32_to_cpu(desc->v_opcode_dtype);
q_msg[i].cookie.mbx.chnl_retval =
le32_to_cpu(desc->v_retval);
q_msg[i].opcode = le16_to_cpu(desc->opcode);
q_msg[i].data_len = le16_to_cpu(desc->datalen);
q_msg[i].status = le16_to_cpu(desc->ret_val);
if (desc->datalen) {
memcpy(q_msg[i].ctx.indirect.context,
&desc->params.indirect, IDPF_INDIRECT_CTX_SIZE);
/* Assign pointer to dma buffer to ctlq_msg array
* to be given to upper layer
*/
q_msg[i].ctx.indirect.payload = cq->bi.rx_buff[ntc];
/* Zero out pointer to DMA buffer info;
* will be repopulated by post buffers API
*/
cq->bi.rx_buff[ntc] = NULL;
} else {
memcpy(q_msg[i].ctx.direct, desc->params.raw,
IDPF_DIRECT_CTX_SIZE);
}
/* Zero out stale data in descriptor */
memset(desc, 0, sizeof(struct idpf_ctlq_desc));
ntc++;
if (ntc == cq->ring_size)
ntc = 0;
}
cq->next_to_clean = ntc;
spin_unlock(&cq->cq_lock);
*num_q_msg = i;
if (*num_q_msg == 0)
err = -ENOMSG;
return err;
}

142
drivers/net/ethernet/intel/idpf/idpf_controlq.h
View File

@ -1,142 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (C) 2023 Intel Corporation */
#ifndef _IDPF_CONTROLQ_H_
#define _IDPF_CONTROLQ_H_
#include <linux/slab.h>
#include "idpf_controlq_api.h"
/* Maximum buffer length for all control queue types */
#define IDPF_CTLQ_MAX_BUF_LEN 4096
#define IDPF_CTLQ_DESC(R, i) \
(&(((struct idpf_ctlq_desc *)((R)->desc_ring.va))[i]))
#define IDPF_CTLQ_DESC_UNUSED(R) \
((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->ring_size) + \
(R)->next_to_clean - (R)->next_to_use - 1))
/* Control Queue default settings */
#define IDPF_CTRL_SQ_CMD_TIMEOUT 250 /* msecs */
struct idpf_ctlq_desc {
/* Control queue descriptor flags */
__le16 flags;
/* Control queue message opcode */
__le16 opcode;
__le16 datalen; /* 0 for direct commands */
union {
__le16 ret_val;
__le16 pfid_vfid;
#define IDPF_CTLQ_DESC_VF_ID_S 0
#define IDPF_CTLQ_DESC_VF_ID_M (0x7FF << IDPF_CTLQ_DESC_VF_ID_S)
#define IDPF_CTLQ_DESC_PF_ID_S 11
#define IDPF_CTLQ_DESC_PF_ID_M (0x1F << IDPF_CTLQ_DESC_PF_ID_S)
};
/* Virtchnl message opcode and virtchnl descriptor type
* v_opcode=[27:0], v_dtype=[31:28]
*/
__le32 v_opcode_dtype;
/* Virtchnl return value */
__le32 v_retval;
union {
struct {
__le32 param0;
__le32 param1;
__le32 param2;
__le32 param3;
} direct;
struct {
__le32 param0;
__le16 sw_cookie;
/* Virtchnl flags */
__le16 v_flags;
__le32 addr_high;
__le32 addr_low;
} indirect;
u8 raw[16];
} params;
};
/* Flags sub-structure
* |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
* |DD |CMP|ERR| * RSV * |FTYPE | *RSV* |RD |VFC|BUF| HOST_ID |
*/
/* command flags and offsets */
#define IDPF_CTLQ_FLAG_DD_S 0
#define IDPF_CTLQ_FLAG_CMP_S 1
#define IDPF_CTLQ_FLAG_ERR_S 2
#define IDPF_CTLQ_FLAG_FTYPE_S 6
#define IDPF_CTLQ_FLAG_RD_S 10
#define IDPF_CTLQ_FLAG_VFC_S 11
#define IDPF_CTLQ_FLAG_BUF_S 12
#define IDPF_CTLQ_FLAG_HOST_ID_S 13
#define IDPF_CTLQ_FLAG_DD BIT(IDPF_CTLQ_FLAG_DD_S) /* 0x1 */
#define IDPF_CTLQ_FLAG_CMP BIT(IDPF_CTLQ_FLAG_CMP_S) /* 0x2 */
#define IDPF_CTLQ_FLAG_ERR BIT(IDPF_CTLQ_FLAG_ERR_S) /* 0x4 */
#define IDPF_CTLQ_FLAG_FTYPE_VM BIT(IDPF_CTLQ_FLAG_FTYPE_S) /* 0x40 */
#define IDPF_CTLQ_FLAG_FTYPE_PF BIT(IDPF_CTLQ_FLAG_FTYPE_S + 1) /* 0x80 */
#define IDPF_CTLQ_FLAG_RD BIT(IDPF_CTLQ_FLAG_RD_S) /* 0x400 */
#define IDPF_CTLQ_FLAG_VFC BIT(IDPF_CTLQ_FLAG_VFC_S) /* 0x800 */
#define IDPF_CTLQ_FLAG_BUF BIT(IDPF_CTLQ_FLAG_BUF_S) /* 0x1000 */
/* Host ID is a special field that has 3b and not a 1b flag */
#define IDPF_CTLQ_FLAG_HOST_ID_M MAKE_MASK(0x7000UL, IDPF_CTLQ_FLAG_HOST_ID_S)
struct idpf_mbxq_desc {
u8 pad[8]; /* CTLQ flags/opcode/len/retval fields */
u32 chnl_opcode; /* avoid confusion with desc->opcode */
u32 chnl_retval; /* ditto for desc->retval */
u32 pf_vf_id; /* used by CP when sending to PF */
};
/* Max number of MMIO regions not including the mailbox and rstat regions in
* the fallback case when the whole bar is mapped.
*/
#define IDPF_MMIO_MAP_FALLBACK_MAX_REMAINING 3
struct idpf_mmio_reg {
void __iomem *vaddr;
resource_size_t addr_start;
resource_size_t addr_len;
};
/* Define the driver hardware struct to replace other control structs as needed
* Align to ctlq_hw_info
*/
struct idpf_hw {
/* Array of remaining LAN BAR regions */
int num_lan_regs;
struct idpf_mmio_reg *lan_regs;
struct idpf_adapter *back;
/* control queue - send and receive */
struct idpf_ctlq_info *asq;
struct idpf_ctlq_info *arq;
/* pci info */
u16 device_id;
u16 vendor_id;
u16 subsystem_device_id;
u16 subsystem_vendor_id;
u8 revision_id;
bool adapter_stopped;
struct list_head cq_list_head;
};
int idpf_ctlq_alloc_ring_res(struct idpf_hw *hw,
struct idpf_ctlq_info *cq);
void idpf_ctlq_dealloc_ring_res(struct idpf_hw *hw, struct idpf_ctlq_info *cq);
/* prototype for functions used for dynamic memory allocation */
void *idpf_alloc_dma_mem(struct idpf_hw *hw, struct idpf_dma_mem *mem,
u64 size);
void idpf_free_dma_mem(struct idpf_hw *hw, struct idpf_dma_mem *mem);
#endif /* _IDPF_CONTROLQ_H_ */

177
drivers/net/ethernet/intel/idpf/idpf_controlq_api.h
View File

@ -1,177 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (C) 2023 Intel Corporation */
#ifndef _IDPF_CONTROLQ_API_H_
#define _IDPF_CONTROLQ_API_H_
#include "idpf_mem.h"
struct idpf_hw;
/* Used for queue init, response and events */
enum idpf_ctlq_type {
IDPF_CTLQ_TYPE_MAILBOX_TX = 0,
IDPF_CTLQ_TYPE_MAILBOX_RX = 1,
IDPF_CTLQ_TYPE_CONFIG_TX = 2,
IDPF_CTLQ_TYPE_CONFIG_RX = 3,
IDPF_CTLQ_TYPE_EVENT_RX = 4,
IDPF_CTLQ_TYPE_RDMA_TX = 5,
IDPF_CTLQ_TYPE_RDMA_RX = 6,
IDPF_CTLQ_TYPE_RDMA_COMPL = 7
};
/* Generic Control Queue Structures */
struct idpf_ctlq_reg {
/* used for queue tracking */
u32 head;
u32 tail;
/* Below applies only to default mb (if present) */
u32 len;
u32 bah;
u32 bal;
u32 len_mask;
u32 len_ena_mask;
u32 head_mask;
};
/* Generic queue msg structure */
struct idpf_ctlq_msg {
u8 vmvf_type; /* represents the source of the message on recv */
#define IDPF_VMVF_TYPE_VF 0
#define IDPF_VMVF_TYPE_VM 1
#define IDPF_VMVF_TYPE_PF 2
u8 host_id;
/* 3b field used only when sending a message to CP - to be used in
* combination with target func_id to route the message
*/
#define IDPF_HOST_ID_MASK 0x7
u16 opcode;
u16 data_len; /* data_len = 0 when no payload is attached */
union {
u16 func_id; /* when sending a message */
u16 status; /* when receiving a message */
};
union {
struct {
u32 chnl_opcode;
u32 chnl_retval;
} mbx;
} cookie;
union {
#define IDPF_DIRECT_CTX_SIZE 16
#define IDPF_INDIRECT_CTX_SIZE 8
/* 16 bytes of context can be provided or 8 bytes of context
* plus the address of a DMA buffer
*/
u8 direct[IDPF_DIRECT_CTX_SIZE];
struct {
u8 context[IDPF_INDIRECT_CTX_SIZE];
struct idpf_dma_mem *payload;
} indirect;
struct {
u32 rsvd;
u16 data;
u16 flags;
} sw_cookie;
} ctx;
};
/* Generic queue info structures */
/* MB, CONFIG and EVENT q do not have extended info */
struct idpf_ctlq_create_info {
enum idpf_ctlq_type type;
int id; /* absolute queue offset passed as input
* -1 for default mailbox if present
*/
u16 len; /* Queue length passed as input */
u16 buf_size; /* buffer size passed as input */
u64 base_address; /* output, HPA of the Queue start */
struct idpf_ctlq_reg reg; /* registers accessed by ctlqs */
int ext_info_size;
void *ext_info; /* Specific to q type */
};
/* Control Queue information */
struct idpf_ctlq_info {
struct list_head cq_list;
enum idpf_ctlq_type cq_type;
int q_id;
spinlock_t cq_lock; /* control queue lock */
/* used for interrupt processing */
u16 next_to_use;
u16 next_to_clean;
u16 next_to_post; /* starting descriptor to post buffers
* to after recev
*/
struct idpf_dma_mem desc_ring; /* descriptor ring memory
* idpf_dma_mem is defined in OSdep.h
*/
union {
struct idpf_dma_mem **rx_buff;
struct idpf_ctlq_msg **tx_msg;
} bi;
u16 buf_size; /* queue buffer size */
u16 ring_size; /* Number of descriptors */
struct idpf_ctlq_reg reg; /* registers accessed by ctlqs */
};
/**
* enum idpf_mbx_opc - PF/VF mailbox commands
* @idpf_mbq_opc_send_msg_to_cp: used by PF or VF to send a message to its CP
* @idpf_mbq_opc_send_msg_to_peer_drv: used by PF or VF to send a message to
* any peer driver
*/
enum idpf_mbx_opc {
idpf_mbq_opc_send_msg_to_cp = 0x0801,
idpf_mbq_opc_send_msg_to_peer_drv = 0x0804,
};
/* API supported for control queue management */
/* Will init all required q including default mb. "q_info" is an array of
* create_info structs equal to the number of control queues to be created.
*/
int idpf_ctlq_init(struct idpf_hw *hw, u8 num_q,
struct idpf_ctlq_create_info *q_info);
/* Allocate and initialize a single control queue, which will be added to the
* control queue list; returns a handle to the created control queue
*/
int idpf_ctlq_add(struct idpf_hw *hw,
struct idpf_ctlq_create_info *qinfo,
struct idpf_ctlq_info **cq);
/* Deinitialize and deallocate a single control queue */
void idpf_ctlq_remove(struct idpf_hw *hw,
struct idpf_ctlq_info *cq);
/* Sends messages to HW and will also free the buffer*/
int idpf_ctlq_send(struct idpf_hw *hw,
struct idpf_ctlq_info *cq,
u16 num_q_msg,
struct idpf_ctlq_msg q_msg[]);
/* Receives messages and called by interrupt handler/polling
* initiated by app/process. Also caller is supposed to free the buffers
*/
int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg,
struct idpf_ctlq_msg *q_msg);
/* Reclaims send descriptors on HW write back */
int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count,
struct idpf_ctlq_msg *msg_status[]);
/* Indicate RX buffers are done being processed */
int idpf_ctlq_post_rx_buffs(struct idpf_hw *hw,
struct idpf_ctlq_info *cq,
u16 *buff_count,
struct idpf_dma_mem **buffs);
/* Will destroy all q including the default mb */
void idpf_ctlq_deinit(struct idpf_hw *hw);
#endif /* _IDPF_CONTROLQ_API_H_ */

169
drivers/net/ethernet/intel/idpf/idpf_controlq_setup.c
View File

@ -1,169 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (C) 2023 Intel Corporation */
#include "idpf_controlq.h"
/**
* idpf_ctlq_alloc_desc_ring - Allocate Control Queue (CQ) rings
* @hw: pointer to hw struct
* @cq: pointer to the specific Control queue
*/
static int idpf_ctlq_alloc_desc_ring(struct idpf_hw *hw,
struct idpf_ctlq_info *cq)
{
size_t size = cq->ring_size * sizeof(struct idpf_ctlq_desc);
cq->desc_ring.va = idpf_alloc_dma_mem(hw, &cq->desc_ring, size);
if (!cq->desc_ring.va)
return -ENOMEM;
return 0;
}
/**
* idpf_ctlq_alloc_bufs - Allocate Control Queue (CQ) buffers
* @hw: pointer to hw struct
* @cq: pointer to the specific Control queue
*
* Allocate the buffer head for all control queues, and if it's a receive
* queue, allocate DMA buffers
*/
static int idpf_ctlq_alloc_bufs(struct idpf_hw *hw,
struct idpf_ctlq_info *cq)
{
int i;
/* Do not allocate DMA buffers for transmit queues */
if (cq->cq_type == IDPF_CTLQ_TYPE_MAILBOX_TX)
return 0;
/* We'll be allocating the buffer info memory first, then we can
* allocate the mapped buffers for the event processing
*/
cq->bi.rx_buff = kzalloc_objs(struct idpf_dma_mem *, cq->ring_size);
if (!cq->bi.rx_buff)
return -ENOMEM;
/* allocate the mapped buffers (except for the last one) */
for (i = 0; i < cq->ring_size - 1; i++) {
struct idpf_dma_mem *bi;
int num = 1; /* number of idpf_dma_mem to be allocated */
cq->bi.rx_buff[i] = kzalloc_objs(struct idpf_dma_mem, num);
if (!cq->bi.rx_buff[i])
goto unwind_alloc_cq_bufs;
bi = cq->bi.rx_buff[i];
bi->va = idpf_alloc_dma_mem(hw, bi, cq->buf_size);
if (!bi->va) {
/* unwind will not free the failed entry */
kfree(cq->bi.rx_buff[i]);
goto unwind_alloc_cq_bufs;
}
}
return 0;
unwind_alloc_cq_bufs:
/* don't try to free the one that failed... */
i--;
for (; i >= 0; i--) {
idpf_free_dma_mem(hw, cq->bi.rx_buff[i]);
kfree(cq->bi.rx_buff[i]);
}
kfree(cq->bi.rx_buff);
return -ENOMEM;
}
/**
* idpf_ctlq_free_desc_ring - Free Control Queue (CQ) rings
* @hw: pointer to hw struct
* @cq: pointer to the specific Control queue
*
* This assumes the posted send buffers have already been cleaned
* and de-allocated
*/
static void idpf_ctlq_free_desc_ring(struct idpf_hw *hw,
struct idpf_ctlq_info *cq)
{
idpf_free_dma_mem(hw, &cq->desc_ring);
}
/**
* idpf_ctlq_free_bufs - Free CQ buffer info elements
* @hw: pointer to hw struct
* @cq: pointer to the specific Control queue
*
* Free the DMA buffers for RX queues, and DMA buffer header for both RX and TX
* queues. The upper layers are expected to manage freeing of TX DMA buffers
*/
static void idpf_ctlq_free_bufs(struct idpf_hw *hw, struct idpf_ctlq_info *cq)
{
void *bi;
if (cq->cq_type == IDPF_CTLQ_TYPE_MAILBOX_RX) {
int i;
/* free DMA buffers for rx queues*/
for (i = 0; i < cq->ring_size; i++) {
if (cq->bi.rx_buff[i]) {
idpf_free_dma_mem(hw, cq->bi.rx_buff[i]);
kfree(cq->bi.rx_buff[i]);
}
}
bi = (void *)cq->bi.rx_buff;
} else {
bi = (void *)cq->bi.tx_msg;
}
/* free the buffer header */
kfree(bi);
}
/**
* idpf_ctlq_dealloc_ring_res - Free memory allocated for control queue
* @hw: pointer to hw struct
* @cq: pointer to the specific Control queue
*
* Free the memory used by the ring, buffers and other related structures
*/
void idpf_ctlq_dealloc_ring_res(struct idpf_hw *hw, struct idpf_ctlq_info *cq)
{
/* free ring buffers and the ring itself */
idpf_ctlq_free_bufs(hw, cq);
idpf_ctlq_free_desc_ring(hw, cq);
}
/**
* idpf_ctlq_alloc_ring_res - allocate memory for descriptor ring and bufs
* @hw: pointer to hw struct
* @cq: pointer to control queue struct
*
* Do *NOT* hold cq_lock when calling this as the memory allocation routines
* called are not going to be atomic context safe
*/
int idpf_ctlq_alloc_ring_res(struct idpf_hw *hw, struct idpf_ctlq_info *cq)
{
int err;
/* allocate the ring memory */
err = idpf_ctlq_alloc_desc_ring(hw, cq);
if (err)
return err;
/* allocate buffers in the rings */
err = idpf_ctlq_alloc_bufs(hw, cq);
if (err)
goto idpf_init_cq_free_ring;
/* success! */
return 0;
idpf_init_cq_free_ring:
idpf_free_dma_mem(hw, &cq->desc_ring);
return err;
}

56
drivers/net/ethernet/intel/idpf/idpf_dev.c
View File

@ -10,44 +10,32 @@
/**
* idpf_ctlq_reg_init - initialize default mailbox registers
* @adapter: adapter structure
* @cq: pointer to the array of create control queues
* @mmio: struct that contains MMIO region info
* @cci: struct where the register offset pointer to be copied to
*/
static void idpf_ctlq_reg_init(struct idpf_adapter *adapter,
struct idpf_ctlq_create_info *cq)
static void idpf_ctlq_reg_init(struct libie_mmio_info *mmio,
struct libie_ctlq_create_info *cci)
{
int i;
struct libie_ctlq_reg *tx_reg = &cci[LIBIE_CTLQ_TYPE_TX].reg;
struct libie_ctlq_reg *rx_reg = &cci[LIBIE_CTLQ_TYPE_RX].reg;
for (i = 0; i < IDPF_NUM_DFLT_MBX_Q; i++) {
struct idpf_ctlq_create_info *ccq = cq + i;
tx_reg->head = libie_pci_get_mmio_addr(mmio, PF_FW_ATQH);
tx_reg->tail = libie_pci_get_mmio_addr(mmio, PF_FW_ATQT);
tx_reg->len = libie_pci_get_mmio_addr(mmio, PF_FW_ATQLEN);
tx_reg->addr_high = libie_pci_get_mmio_addr(mmio, PF_FW_ATQBAH);
tx_reg->addr_low = libie_pci_get_mmio_addr(mmio, PF_FW_ATQBAL);
tx_reg->len_mask = PF_FW_ATQLEN_ATQLEN_M;
tx_reg->len_ena_mask = PF_FW_ATQLEN_ATQENABLE_M;
tx_reg->head_mask = PF_FW_ATQH_ATQH_M;
switch (ccq->type) {
case IDPF_CTLQ_TYPE_MAILBOX_TX:
/* set head and tail registers in our local struct */
ccq->reg.head = PF_FW_ATQH;
ccq->reg.tail = PF_FW_ATQT;
ccq->reg.len = PF_FW_ATQLEN;
ccq->reg.bah = PF_FW_ATQBAH;
ccq->reg.bal = PF_FW_ATQBAL;
ccq->reg.len_mask = PF_FW_ATQLEN_ATQLEN_M;
ccq->reg.len_ena_mask = PF_FW_ATQLEN_ATQENABLE_M;
ccq->reg.head_mask = PF_FW_ATQH_ATQH_M;
break;
case IDPF_CTLQ_TYPE_MAILBOX_RX:
/* set head and tail registers in our local struct */
ccq->reg.head = PF_FW_ARQH;
ccq->reg.tail = PF_FW_ARQT;
ccq->reg.len = PF_FW_ARQLEN;
ccq->reg.bah = PF_FW_ARQBAH;
ccq->reg.bal = PF_FW_ARQBAL;
ccq->reg.len_mask = PF_FW_ARQLEN_ARQLEN_M;
ccq->reg.len_ena_mask = PF_FW_ARQLEN_ARQENABLE_M;
ccq->reg.head_mask = PF_FW_ARQH_ARQH_M;
break;
default:
break;
}
}
rx_reg->head = libie_pci_get_mmio_addr(mmio, PF_FW_ARQH);
rx_reg->tail = libie_pci_get_mmio_addr(mmio, PF_FW_ARQT);
rx_reg->len = libie_pci_get_mmio_addr(mmio, PF_FW_ARQLEN);
rx_reg->addr_high = libie_pci_get_mmio_addr(mmio, PF_FW_ARQBAH);
rx_reg->addr_low = libie_pci_get_mmio_addr(mmio, PF_FW_ARQBAL);
rx_reg->len_mask = PF_FW_ARQLEN_ARQLEN_M;
rx_reg->len_ena_mask = PF_FW_ARQLEN_ARQENABLE_M;
rx_reg->head_mask = PF_FW_ARQH_ARQH_M;
}
/**

28
drivers/net/ethernet/intel/idpf/idpf_ethtool.c
View File

@ -225,7 +225,7 @@ static int idpf_add_flow_steer(struct net_device *netdev,
spin_unlock_bh(&vport_config->flow_steer_list_lock);
if (err)
goto out;
goto out_free_fltr;
rule->vport_id = cpu_to_le32(vport->vport_id);
rule->count = cpu_to_le32(1);
@ -252,17 +252,15 @@ static int idpf_add_flow_steer(struct net_device *netdev,
break;
default:
err = -EINVAL;
goto out;
goto out_free_fltr;
}
err = idpf_add_del_fsteer_filters(vport->adapter, rule,
VIRTCHNL2_OP_ADD_FLOW_RULE);
if (err)
goto out;
if (info->status != cpu_to_le32(VIRTCHNL2_FLOW_RULE_SUCCESS)) {
err = -EIO;
goto out;
if (err) {
/* virtchnl2 rule is already consumed */
kfree(fltr);
return err;
}
/* Save a copy of the user's flow spec so ethtool can later retrieve it */
@ -274,9 +272,10 @@ static int idpf_add_flow_steer(struct net_device *netdev,
user_config->num_fsteer_fltrs++;
spin_unlock_bh(&vport_config->flow_steer_list_lock);
goto out_free_rule;
out:
return 0;
out_free_fltr:
kfree(fltr);
out_free_rule:
kfree(rule);
@ -319,12 +318,7 @@ static int idpf_del_flow_steer(struct net_device *netdev,
err = idpf_add_del_fsteer_filters(vport->adapter, rule,
VIRTCHNL2_OP_DEL_FLOW_RULE);
if (err)
goto out;
if (info->status != cpu_to_le32(VIRTCHNL2_FLOW_RULE_SUCCESS)) {
err = -EIO;
goto out;
}
return err;
spin_lock_bh(&vport_config->flow_steer_list_lock);
list_for_each_entry_safe(f, iter,
@ -340,8 +334,6 @@ static int idpf_del_flow_steer(struct net_device *netdev,
out_unlock:
spin_unlock_bh(&vport_config->flow_steer_list_lock);
out:
kfree(rule);
return err;
}

51
drivers/net/ethernet/intel/idpf/idpf_lib.c
View File

@ -1371,6 +1371,7 @@ void idpf_statistics_task(struct work_struct *work)
*/
void idpf_mbx_task(struct work_struct *work)
{
struct libie_ctlq_xn_recv_params xn_params;
struct idpf_adapter *adapter;
adapter = container_of(work, struct idpf_adapter, mbx_task.work);
@ -1381,7 +1382,14 @@ void idpf_mbx_task(struct work_struct *work)
queue_delayed_work(adapter->mbx_wq, &adapter->mbx_task,
usecs_to_jiffies(300));
idpf_recv_mb_msg(adapter, adapter->hw.arq);
xn_params = (struct libie_ctlq_xn_recv_params) {
.xnm = adapter->xnm,
.ctlq = adapter->arq,
.ctlq_msg_handler = idpf_recv_event_msg,
.budget = LIBIE_CTLQ_MAX_XN_ENTRIES,
};
libie_ctlq_xn_recv(&xn_params);
}
/**
@ -1984,7 +1992,8 @@ void idpf_vc_event_task(struct work_struct *work)
return;
func_reset:
idpf_vc_xn_shutdown(adapter->vcxn_mngr);
if (adapter->xnm)
libie_ctlq_xn_shutdown(adapter->xnm);
drv_load:
set_bit(IDPF_HR_RESET_IN_PROG, adapter->flags);
idpf_init_hard_reset(adapter);
@ -2567,44 +2576,6 @@ static int idpf_set_mac(struct net_device *netdev, void *p)
return err;
}
/**
* idpf_alloc_dma_mem - Allocate dma memory
* @hw: pointer to hw struct
* @mem: pointer to dma_mem struct
* @size: size of the memory to allocate
*/
void *idpf_alloc_dma_mem(struct idpf_hw *hw, struct idpf_dma_mem *mem, u64 size)
{
struct idpf_adapter *adapter = hw->back;
size_t sz = ALIGN(size, 4096);
/* The control queue resources are freed under a spinlock, contiguous
* pages will avoid IOMMU remapping and the use vmap (and vunmap in
* dma_free_*() path.
*/
mem->va = dma_alloc_attrs(&adapter->pdev->dev, sz, &mem->pa,
GFP_KERNEL, DMA_ATTR_FORCE_CONTIGUOUS);
mem->size = sz;
return mem->va;
}
/**
* idpf_free_dma_mem - Free the allocated dma memory
* @hw: pointer to hw struct
* @mem: pointer to dma_mem struct
*/
void idpf_free_dma_mem(struct idpf_hw *hw, struct idpf_dma_mem *mem)
{
struct idpf_adapter *adapter = hw->back;
dma_free_attrs(&adapter->pdev->dev, mem->size,
mem->va, mem->pa, DMA_ATTR_FORCE_CONTIGUOUS);
mem->size = 0;
mem->va = NULL;
mem->pa = 0;
}
static int idpf_hwtstamp_set(struct net_device *netdev,
struct kernel_hwtstamp_config *config,
struct netlink_ext_ack *extack)

3
drivers/net/ethernet/intel/idpf/idpf_main.c
View File

@ -170,8 +170,6 @@ static void idpf_remove(struct pci_dev *pdev)
adapter->vport_config = NULL;
kfree(adapter->netdevs);
adapter->netdevs = NULL;
kfree(adapter->vcxn_mngr);
adapter->vcxn_mngr = NULL;
mutex_destroy(&adapter->vport_ctrl_lock);
mutex_destroy(&adapter->vector_lock);
@ -239,7 +237,6 @@ static int idpf_cfg_device(struct idpf_adapter *adapter)
pci_dbg(pdev, "PCIe PTM is not supported by PCIe bus/controller\n");
pci_set_drvdata(pdev, adapter);
adapter->hw.back = adapter;
return 0;
}

20
drivers/net/ethernet/intel/idpf/idpf_mem.h
View File

@ -1,20 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (C) 2023 Intel Corporation */
#ifndef _IDPF_MEM_H_
#define _IDPF_MEM_H_
#include <linux/io.h>
struct idpf_dma_mem {
void *va;
dma_addr_t pa;
size_t size;
};
#define idpf_mbx_wr32(a, reg, value) writel((value), ((a)->mbx.vaddr + (reg)))
#define idpf_mbx_rd32(a, reg) readl((a)->mbx.vaddr + (reg))
#define idpf_mbx_wr64(a, reg, value) writeq((value), ((a)->mbx.vaddr + (reg)))
#define idpf_mbx_rd64(a, reg) readq((a)->mbx.vaddr + (reg))
#endif /* _IDPF_MEM_H_ */

2
drivers/net/ethernet/intel/idpf/idpf_txrx.h
View File

@ -236,7 +236,7 @@ enum idpf_tx_ctx_desc_eipt_offload {
(sizeof(u16) * IDPF_RX_MAX_PTYPE_PROTO_IDS))
#define IDPF_RX_PTYPE_HDR_SZ sizeof(struct virtchnl2_get_ptype_info)
#define IDPF_RX_MAX_PTYPES_PER_BUF \
DIV_ROUND_DOWN_ULL((IDPF_CTLQ_MAX_BUF_LEN - IDPF_RX_PTYPE_HDR_SZ), \
DIV_ROUND_DOWN_ULL(LIBIE_CTLQ_MAX_BUF_LEN - IDPF_RX_PTYPE_HDR_SZ, \
IDPF_RX_MAX_PTYPE_SZ)
#define IDPF_GET_PTYPE_SIZE(p) struct_size((p), proto_id, (p)->proto_id_count)

59
drivers/net/ethernet/intel/idpf/idpf_vf_dev.c
View File

@ -9,42 +9,32 @@
/**
* idpf_vf_ctlq_reg_init - initialize default mailbox registers
* @adapter: adapter structure
* @cq: pointer to the array of create control queues
* @mmio: struct that contains MMIO region info
* @cci: struct where the register offset pointer to be copied to
*/
static void idpf_vf_ctlq_reg_init(struct idpf_adapter *adapter,
struct idpf_ctlq_create_info *cq)
static void idpf_vf_ctlq_reg_init(struct libie_mmio_info *mmio,
struct libie_ctlq_create_info *cci)
{
for (int i = 0; i < IDPF_NUM_DFLT_MBX_Q; i++) {
struct idpf_ctlq_create_info *ccq = cq + i;
struct libie_ctlq_reg *tx_reg = &cci[LIBIE_CTLQ_TYPE_TX].reg;
struct libie_ctlq_reg *rx_reg = &cci[LIBIE_CTLQ_TYPE_RX].reg;
switch (ccq->type) {
case IDPF_CTLQ_TYPE_MAILBOX_TX:
/* set head and tail registers in our local struct */
ccq->reg.head = VF_ATQH;
ccq->reg.tail = VF_ATQT;
ccq->reg.len = VF_ATQLEN;
ccq->reg.bah = VF_ATQBAH;
ccq->reg.bal = VF_ATQBAL;
ccq->reg.len_mask = VF_ATQLEN_ATQLEN_M;
ccq->reg.len_ena_mask = VF_ATQLEN_ATQENABLE_M;
ccq->reg.head_mask = VF_ATQH_ATQH_M;
break;
case IDPF_CTLQ_TYPE_MAILBOX_RX:
/* set head and tail registers in our local struct */
ccq->reg.head = VF_ARQH;
ccq->reg.tail = VF_ARQT;
ccq->reg.len = VF_ARQLEN;
ccq->reg.bah = VF_ARQBAH;
ccq->reg.bal = VF_ARQBAL;
ccq->reg.len_mask = VF_ARQLEN_ARQLEN_M;
ccq->reg.len_ena_mask = VF_ARQLEN_ARQENABLE_M;
ccq->reg.head_mask = VF_ARQH_ARQH_M;
break;
default:
break;
}
}
tx_reg->head = libie_pci_get_mmio_addr(mmio, VF_ATQH);
tx_reg->tail = libie_pci_get_mmio_addr(mmio, VF_ATQT);
tx_reg->len = libie_pci_get_mmio_addr(mmio, VF_ATQLEN);
tx_reg->addr_high = libie_pci_get_mmio_addr(mmio, VF_ATQBAH);
tx_reg->addr_low = libie_pci_get_mmio_addr(mmio, VF_ATQBAL);
tx_reg->len_mask = VF_ATQLEN_ATQLEN_M;
tx_reg->len_ena_mask = VF_ATQLEN_ATQENABLE_M;
tx_reg->head_mask = VF_ATQH_ATQH_M;
rx_reg->head = libie_pci_get_mmio_addr(mmio, VF_ARQH);
rx_reg->tail = libie_pci_get_mmio_addr(mmio, VF_ARQT);
rx_reg->len = libie_pci_get_mmio_addr(mmio, VF_ARQLEN);
rx_reg->addr_high = libie_pci_get_mmio_addr(mmio, VF_ARQBAH);
rx_reg->addr_low = libie_pci_get_mmio_addr(mmio, VF_ARQBAL);
rx_reg->len_mask = VF_ARQLEN_ARQLEN_M;
rx_reg->len_ena_mask = VF_ARQLEN_ARQENABLE_M;
rx_reg->head_mask = VF_ARQH_ARQH_M;
}
/**
@ -160,8 +150,7 @@ static void idpf_vf_trigger_reset(struct idpf_adapter *adapter,
/* Do not send VIRTCHNL2_OP_RESET_VF message on driver unload */
if (trig_cause == IDPF_HR_FUNC_RESET &&
!test_bit(IDPF_REMOVE_IN_PROG, adapter->flags))
idpf_send_mb_msg(adapter, adapter->hw.asq,
VIRTCHNL2_OP_RESET_VF, 0, NULL, 0);
idpf_send_vf_reset_msg(adapter);
}
/**

1625
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
View File

File diff suppressed because it is too large Load Diff

113
drivers/net/ethernet/intel/idpf/idpf_virtchnl.h
View File

@ -7,86 +7,6 @@
#include <linux/net/intel/virtchnl2.h>
#define IDPF_VC_XN_DEFAULT_TIMEOUT_MSEC (60 * 1000)
#define IDPF_VC_XN_IDX_M GENMASK(7, 0)
#define IDPF_VC_XN_SALT_M GENMASK(15, 8)
#define IDPF_VC_XN_RING_LEN U8_MAX
/**
* enum idpf_vc_xn_state - Virtchnl transaction status
* @IDPF_VC_XN_IDLE: not expecting a reply, ready to be used
* @IDPF_VC_XN_WAITING: expecting a reply, not yet received
* @IDPF_VC_XN_COMPLETED_SUCCESS: a reply was expected and received, buffer
* updated
* @IDPF_VC_XN_COMPLETED_FAILED: a reply was expected and received, but there
* was an error, buffer not updated
* @IDPF_VC_XN_SHUTDOWN: transaction object cannot be used, VC torn down
* @IDPF_VC_XN_ASYNC: transaction sent asynchronously and doesn't have the
* return context; a callback may be provided to handle
* return
*/
enum idpf_vc_xn_state {
IDPF_VC_XN_IDLE = 1,
IDPF_VC_XN_WAITING,
IDPF_VC_XN_COMPLETED_SUCCESS,
IDPF_VC_XN_COMPLETED_FAILED,
IDPF_VC_XN_SHUTDOWN,
IDPF_VC_XN_ASYNC,
};
struct idpf_vc_xn;
/* Callback for asynchronous messages */
typedef int (*async_vc_cb) (struct idpf_adapter *, struct idpf_vc_xn *,
const struct idpf_ctlq_msg *);
/**
* struct idpf_vc_xn - Data structure representing virtchnl transactions
* @completed: virtchnl event loop uses that to signal when a reply is
* available, uses kernel completion API
* @lock: protects the transaction state fields below
* @state: virtchnl event loop stores the data below, protected by @lock
* @reply_sz: Original size of reply, may be > reply_buf.iov_len; it will be
* truncated on its way to the receiver thread according to
* reply_buf.iov_len.
* @reply: Reference to the buffer(s) where the reply data should be written
* to. May be 0-length (then NULL address permitted) if the reply data
* should be ignored.
* @async_handler: if sent asynchronously, a callback can be provided to handle
* the reply when it's received
* @vc_op: corresponding opcode sent with this transaction
* @idx: index used as retrieval on reply receive, used for cookie
* @salt: changed every message to make unique, used for cookie
*/
struct idpf_vc_xn {
struct completion completed;
spinlock_t lock;
enum idpf_vc_xn_state state;
size_t reply_sz;
struct kvec reply;
async_vc_cb async_handler;
u32 vc_op;
u8 idx;
u8 salt;
};
/**
* struct idpf_vc_xn_params - Parameters for executing transaction
* @send_buf: kvec for send buffer
* @recv_buf: kvec for recv buffer, may be NULL, must then have zero length
* @timeout_ms: timeout to wait for reply
* @async: send message asynchronously, will not wait on completion
* @async_handler: If sent asynchronously, optional callback handler. The user
* must be careful when using async handlers as the memory for
* the recv_buf _cannot_ be on stack if this is async.
* @vc_op: virtchnl op to send
*/
struct idpf_vc_xn_params {
struct kvec send_buf;
struct kvec recv_buf;
int timeout_ms;
bool async;
async_vc_cb async_handler;
u32 vc_op;
};
struct idpf_adapter;
struct idpf_netdev_priv;
@ -96,8 +16,6 @@ struct idpf_vport_max_q;
struct idpf_vport_config;
struct idpf_vport_user_config_data;
ssize_t idpf_vc_xn_exec(struct idpf_adapter *adapter,
const struct idpf_vc_xn_params *params);
int idpf_init_dflt_mbx(struct idpf_adapter *adapter);
void idpf_deinit_dflt_mbx(struct idpf_adapter *adapter);
int idpf_vc_core_init(struct idpf_adapter *adapter);
@ -124,12 +42,36 @@ bool idpf_sideband_action_ena(struct idpf_vport *vport,
struct ethtool_rx_flow_spec *fsp);
unsigned int idpf_fsteer_max_rules(struct idpf_vport *vport);
int idpf_recv_mb_msg(struct idpf_adapter *adapter, struct idpf_ctlq_info *arq);
int idpf_send_mb_msg(struct idpf_adapter *adapter, struct idpf_ctlq_info *asq,
u32 op, u16 msg_size, u8 *msg, u16 cookie);
void idpf_recv_event_msg(struct libie_ctlq_ctx *ctx,
struct libie_ctlq_msg *ctlq_msg);
int idpf_send_mb_msg(struct idpf_adapter *adapter,
struct libie_ctlq_xn_send_params *xn_params,
void *send_buf, size_t send_buf_size);
int idpf_send_mb_msg_kfree(struct idpf_adapter *adapter,
struct libie_ctlq_xn_send_params *xn_params,
void *send_buf, size_t send_buf_size);
void idpf_send_vf_reset_msg(struct idpf_adapter *adapter);
bool idpf_mmio_region_non_static(struct libie_mmio_info *mmio_info,
struct libie_pci_mmio_region *reg);
/**
* idpf_send_mb_msg_stack - send a mailbox message from an on-stack buffer
* @adapter: driver specific private structure
* @xn_params: Xn send parameters to fill
* @ptr: pointer to the on-stack message object to send
*
* Send size is deduced based on the pointer type.
*
* Return: %0 on success, -%errno on failure.
*/
#define idpf_send_mb_msg_stack(adapter, xn_params, ptr) \
({ \
typeof(ptr) __ptr = (ptr); \
\
static_assert(sizeof(*__ptr) <= LIBIE_CP_TX_COPYBREAK); \
idpf_send_mb_msg(adapter, xn_params, __ptr, sizeof(*__ptr)); \
})
struct idpf_queue_ptr {
enum virtchnl2_queue_type type;
union {
@ -214,7 +156,6 @@ int idpf_send_set_rss_key_msg(struct idpf_adapter *adapter,
struct idpf_rss_data *rss_data, u32 vport_id);
int idpf_send_set_rss_lut_msg(struct idpf_adapter *adapter,
struct idpf_rss_data *rss_data, u32 vport_id);
void idpf_vc_xn_shutdown(struct idpf_vc_xn_manager *vcxn_mngr);
int idpf_idc_rdma_vc_send_sync(struct iidc_rdma_core_dev_info *cdev_info,
u8 *send_msg, u16 msg_size,
u8 *recv_msg, u16 *recv_len);

252
drivers/net/ethernet/intel/idpf/idpf_virtchnl_ptp.c
View File

@ -15,7 +15,6 @@
*/
int idpf_ptp_get_caps(struct idpf_adapter *adapter)
{
struct virtchnl2_ptp_get_caps *recv_ptp_caps_msg __free(kfree) = NULL;
struct virtchnl2_ptp_get_caps send_ptp_caps_msg = {
.caps = cpu_to_le32(VIRTCHNL2_CAP_PTP_GET_DEVICE_CLK_TIME |
VIRTCHNL2_CAP_PTP_GET_DEVICE_CLK_TIME_MB |
@ -24,34 +23,33 @@ int idpf_ptp_get_caps(struct idpf_adapter *adapter)
VIRTCHNL2_CAP_PTP_ADJ_DEVICE_CLK_MB |
VIRTCHNL2_CAP_PTP_TX_TSTAMPS_MB)
};
struct idpf_vc_xn_params xn_params = {
.vc_op = VIRTCHNL2_OP_PTP_GET_CAPS,
.send_buf.iov_base = &send_ptp_caps_msg,
.send_buf.iov_len = sizeof(send_ptp_caps_msg),
struct libie_ctlq_xn_send_params xn_params = {
.chnl_opcode = VIRTCHNL2_OP_PTP_GET_CAPS,
.timeout_ms = IDPF_VC_XN_DEFAULT_TIMEOUT_MSEC,
};
struct virtchnl2_ptp_cross_time_reg_offsets cross_tstamp_offsets;
struct libie_mmio_info *mmio = &adapter->ctlq_ctx.mmio_info;
struct virtchnl2_ptp_clk_adj_reg_offsets clk_adj_offsets;
struct virtchnl2_ptp_clk_reg_offsets clock_offsets;
struct virtchnl2_ptp_get_caps *recv_ptp_caps_msg;
struct idpf_ptp_secondary_mbx *scnd_mbx;
struct idpf_ptp *ptp = adapter->ptp;
enum idpf_ptp_access access_type;
u32 temp_offset;
int reply_sz;
size_t reply_sz;
int err;
recv_ptp_caps_msg = kzalloc_obj(struct virtchnl2_ptp_get_caps);
if (!recv_ptp_caps_msg)
return -ENOMEM;
err = idpf_send_mb_msg_stack(adapter, &xn_params, &send_ptp_caps_msg);
if (err)
return err;
xn_params.recv_buf.iov_base = recv_ptp_caps_msg;
xn_params.recv_buf.iov_len = sizeof(*recv_ptp_caps_msg);
reply_sz = xn_params.recv_mem.iov_len;
if (reply_sz != sizeof(*recv_ptp_caps_msg)) {
err = -EIO;
goto free_resp;
}
reply_sz = idpf_vc_xn_exec(adapter, &xn_params);
if (reply_sz < 0)
return reply_sz;
else if (reply_sz != sizeof(*recv_ptp_caps_msg))
return -EIO;
recv_ptp_caps_msg = xn_params.recv_mem.iov_base;
ptp->caps = le32_to_cpu(recv_ptp_caps_msg->caps);
ptp->base_incval = le64_to_cpu(recv_ptp_caps_msg->base_incval);
@ -112,7 +110,7 @@ int idpf_ptp_get_caps(struct idpf_adapter *adapter)
discipline_clock:
access_type = ptp->adj_dev_clk_time_access;
if (access_type != IDPF_PTP_DIRECT)
return 0;
goto free_resp;
clk_adj_offsets = recv_ptp_caps_msg->clk_adj_offsets;
@ -145,7 +143,9 @@ int idpf_ptp_get_caps(struct idpf_adapter *adapter)
ptp->dev_clk_regs.phy_shadj_h =
libie_pci_get_mmio_addr(mmio, temp_offset);
return 0;
free_resp:
libie_ctlq_release_rx_buf(&xn_params.recv_mem);
return err;
}
/**
@ -160,28 +160,34 @@ int idpf_ptp_get_caps(struct idpf_adapter *adapter)
int idpf_ptp_get_dev_clk_time(struct idpf_adapter *adapter,
struct idpf_ptp_dev_timers *dev_clk_time)
{
struct virtchnl2_ptp_get_dev_clk_time *get_dev_clk_time_resp;
struct virtchnl2_ptp_get_dev_clk_time get_dev_clk_time_msg;
struct idpf_vc_xn_params xn_params = {
.vc_op = VIRTCHNL2_OP_PTP_GET_DEV_CLK_TIME,
.send_buf.iov_base = &get_dev_clk_time_msg,
.send_buf.iov_len = sizeof(get_dev_clk_time_msg),
.recv_buf.iov_base = &get_dev_clk_time_msg,
.recv_buf.iov_len = sizeof(get_dev_clk_time_msg),
struct libie_ctlq_xn_send_params xn_params = {
.chnl_opcode = VIRTCHNL2_OP_PTP_GET_DEV_CLK_TIME,
.timeout_ms = IDPF_VC_XN_DEFAULT_TIMEOUT_MSEC,
};
int reply_sz;
size_t reply_sz;
u64 dev_time;
int err;
reply_sz = idpf_vc_xn_exec(adapter, &xn_params);
if (reply_sz < 0)
return reply_sz;
if (reply_sz != sizeof(get_dev_clk_time_msg))
return -EIO;
err = idpf_send_mb_msg_stack(adapter, &xn_params,
&get_dev_clk_time_msg);
if (err)
return err;
dev_time = le64_to_cpu(get_dev_clk_time_msg.dev_time_ns);
reply_sz = xn_params.recv_mem.iov_len;
if (reply_sz != sizeof(*get_dev_clk_time_resp)) {
err = -EIO;
goto free_resp;
}
get_dev_clk_time_resp = xn_params.recv_mem.iov_base;
dev_time = le64_to_cpu(get_dev_clk_time_resp->dev_time_ns);
dev_clk_time->dev_clk_time_ns = dev_time;
return 0;
free_resp:
libie_ctlq_release_rx_buf(&xn_params.recv_mem);
return err;
}
/**
@ -197,27 +203,29 @@ int idpf_ptp_get_dev_clk_time(struct idpf_adapter *adapter,
int idpf_ptp_get_cross_time(struct idpf_adapter *adapter,
struct idpf_ptp_dev_timers *cross_time)
{
struct virtchnl2_ptp_get_cross_time cross_time_msg;
struct idpf_vc_xn_params xn_params = {
.vc_op = VIRTCHNL2_OP_PTP_GET_CROSS_TIME,
.send_buf.iov_base = &cross_time_msg,
.send_buf.iov_len = sizeof(cross_time_msg),
.recv_buf.iov_base = &cross_time_msg,
.recv_buf.iov_len = sizeof(cross_time_msg),
struct virtchnl2_ptp_get_cross_time cross_time_send, *cross_time_recv;
struct libie_ctlq_xn_send_params xn_params = {
.chnl_opcode = VIRTCHNL2_OP_PTP_GET_CROSS_TIME,
.timeout_ms = IDPF_VC_XN_DEFAULT_TIMEOUT_MSEC,
};
int reply_sz;
int err = 0;
reply_sz = idpf_vc_xn_exec(adapter, &xn_params);
if (reply_sz < 0)
return reply_sz;
if (reply_sz != sizeof(cross_time_msg))
return -EIO;
err = idpf_send_mb_msg_stack(adapter, &xn_params, &cross_time_send);
if (err)
return err;
cross_time->dev_clk_time_ns = le64_to_cpu(cross_time_msg.dev_time_ns);
cross_time->sys_time_ns = le64_to_cpu(cross_time_msg.sys_time_ns);
if (xn_params.recv_mem.iov_len != sizeof(*cross_time_recv)) {
err = -EIO;
goto free_resp;
}
return 0;
cross_time_recv = xn_params.recv_mem.iov_base;
cross_time->dev_clk_time_ns = le64_to_cpu(cross_time_recv->dev_time_ns);
cross_time->sys_time_ns = le64_to_cpu(cross_time_recv->sys_time_ns);
free_resp:
libie_ctlq_release_rx_buf(&xn_params.recv_mem);
return err;
}
/**
@ -234,23 +242,18 @@ int idpf_ptp_set_dev_clk_time(struct idpf_adapter *adapter, u64 time)
struct virtchnl2_ptp_set_dev_clk_time set_dev_clk_time_msg = {
.dev_time_ns = cpu_to_le64(time),
};
struct idpf_vc_xn_params xn_params = {
.vc_op = VIRTCHNL2_OP_PTP_SET_DEV_CLK_TIME,
.send_buf.iov_base = &set_dev_clk_time_msg,
.send_buf.iov_len = sizeof(set_dev_clk_time_msg),
.recv_buf.iov_base = &set_dev_clk_time_msg,
.recv_buf.iov_len = sizeof(set_dev_clk_time_msg),
struct libie_ctlq_xn_send_params xn_params = {
.chnl_opcode = VIRTCHNL2_OP_PTP_SET_DEV_CLK_TIME,
.timeout_ms = IDPF_VC_XN_DEFAULT_TIMEOUT_MSEC,
};
int reply_sz;
int err;
reply_sz = idpf_vc_xn_exec(adapter, &xn_params);
if (reply_sz < 0)
return reply_sz;
if (reply_sz != sizeof(set_dev_clk_time_msg))
return -EIO;
err = idpf_send_mb_msg_stack(adapter, &xn_params,
&set_dev_clk_time_msg);
if (!err)
libie_ctlq_release_rx_buf(&xn_params.recv_mem);
return 0;
return err;
}
/**
@ -267,23 +270,18 @@ int idpf_ptp_adj_dev_clk_time(struct idpf_adapter *adapter, s64 delta)
struct virtchnl2_ptp_adj_dev_clk_time adj_dev_clk_time_msg = {
.delta = cpu_to_le64(delta),
};
struct idpf_vc_xn_params xn_params = {
.vc_op = VIRTCHNL2_OP_PTP_ADJ_DEV_CLK_TIME,
.send_buf.iov_base = &adj_dev_clk_time_msg,
.send_buf.iov_len = sizeof(adj_dev_clk_time_msg),
.recv_buf.iov_base = &adj_dev_clk_time_msg,
.recv_buf.iov_len = sizeof(adj_dev_clk_time_msg),
struct libie_ctlq_xn_send_params xn_params = {
.chnl_opcode = VIRTCHNL2_OP_PTP_ADJ_DEV_CLK_TIME,
.timeout_ms = IDPF_VC_XN_DEFAULT_TIMEOUT_MSEC,
};
int reply_sz;
int err;
reply_sz = idpf_vc_xn_exec(adapter, &xn_params);
if (reply_sz < 0)
return reply_sz;
if (reply_sz != sizeof(adj_dev_clk_time_msg))
return -EIO;
err = idpf_send_mb_msg_stack(adapter, &xn_params,
&adj_dev_clk_time_msg);
if (!err)
libie_ctlq_release_rx_buf(&xn_params.recv_mem);
return 0;
return err;
}
/**
@ -301,23 +299,18 @@ int idpf_ptp_adj_dev_clk_fine(struct idpf_adapter *adapter, u64 incval)
struct virtchnl2_ptp_adj_dev_clk_fine adj_dev_clk_fine_msg = {
.incval = cpu_to_le64(incval),
};
struct idpf_vc_xn_params xn_params = {
.vc_op = VIRTCHNL2_OP_PTP_ADJ_DEV_CLK_FINE,
.send_buf.iov_base = &adj_dev_clk_fine_msg,
.send_buf.iov_len = sizeof(adj_dev_clk_fine_msg),
.recv_buf.iov_base = &adj_dev_clk_fine_msg,
.recv_buf.iov_len = sizeof(adj_dev_clk_fine_msg),
struct libie_ctlq_xn_send_params xn_params = {
.chnl_opcode = VIRTCHNL2_OP_PTP_ADJ_DEV_CLK_FINE,
.timeout_ms = IDPF_VC_XN_DEFAULT_TIMEOUT_MSEC,
};
int reply_sz;
int err;
reply_sz = idpf_vc_xn_exec(adapter, &xn_params);
if (reply_sz < 0)
return reply_sz;
if (reply_sz != sizeof(adj_dev_clk_fine_msg))
return -EIO;
err = idpf_send_mb_msg_stack(adapter, &xn_params,
&adj_dev_clk_fine_msg);
if (!err)
libie_ctlq_release_rx_buf(&xn_params.recv_mem);
return 0;
return err;
}
/**
@ -336,18 +329,16 @@ int idpf_ptp_get_vport_tstamps_caps(struct idpf_vport *vport)
struct virtchnl2_ptp_tx_tstamp_latch_caps tx_tstamp_latch_caps;
struct idpf_ptp_vport_tx_tstamp_caps *tstamp_caps;
struct idpf_ptp_tx_tstamp *ptp_tx_tstamp, *tmp;
struct idpf_vc_xn_params xn_params = {
.vc_op = VIRTCHNL2_OP_PTP_GET_VPORT_TX_TSTAMP_CAPS,
.send_buf.iov_base = &send_tx_tstamp_caps,
.send_buf.iov_len = sizeof(send_tx_tstamp_caps),
.recv_buf.iov_len = IDPF_CTLQ_MAX_BUF_LEN,
struct libie_ctlq_xn_send_params xn_params = {
.chnl_opcode = VIRTCHNL2_OP_PTP_GET_VPORT_TX_TSTAMP_CAPS,
.timeout_ms = IDPF_VC_XN_DEFAULT_TIMEOUT_MSEC,
};
enum idpf_ptp_access tstamp_access, get_dev_clk_access;
struct idpf_ptp *ptp = vport->adapter->ptp;
struct list_head *head;
int err = 0, reply_sz;
size_t reply_sz;
u16 num_latches;
int err = 0;
u32 size;
if (!ptp)
@ -359,19 +350,19 @@ int idpf_ptp_get_vport_tstamps_caps(struct idpf_vport *vport)
get_dev_clk_access == IDPF_PTP_NONE)
return -EOPNOTSUPP;
rcv_tx_tstamp_caps = kzalloc(IDPF_CTLQ_MAX_BUF_LEN, GFP_KERNEL);
if (!rcv_tx_tstamp_caps)
return -ENOMEM;
send_tx_tstamp_caps.vport_id = cpu_to_le32(vport->vport_id);
xn_params.recv_buf.iov_base = rcv_tx_tstamp_caps;
reply_sz = idpf_vc_xn_exec(vport->adapter, &xn_params);
if (reply_sz < 0) {
err = reply_sz;
err = idpf_send_mb_msg_stack(vport->adapter, &xn_params,
&send_tx_tstamp_caps);
if (err)
return err;
rcv_tx_tstamp_caps = xn_params.recv_mem.iov_base;
reply_sz = xn_params.recv_mem.iov_len;
if (reply_sz < sizeof(*rcv_tx_tstamp_caps)) {
err = -EIO;
goto get_tstamp_caps_out;
}
num_latches = le16_to_cpu(rcv_tx_tstamp_caps->num_latches);
size = struct_size(rcv_tx_tstamp_caps, tstamp_latches, num_latches);
if (reply_sz != size) {
@ -426,7 +417,7 @@ int idpf_ptp_get_vport_tstamps_caps(struct idpf_vport *vport)
}
vport->tx_tstamp_caps = tstamp_caps;
kfree(rcv_tx_tstamp_caps);
libie_ctlq_release_rx_buf(&xn_params.recv_mem);
return 0;
@ -439,7 +430,7 @@ int idpf_ptp_get_vport_tstamps_caps(struct idpf_vport *vport)
kfree(tstamp_caps);
get_tstamp_caps_out:
kfree(rcv_tx_tstamp_caps);
libie_ctlq_release_rx_buf(&xn_params.recv_mem);
return err;
}
@ -536,9 +527,9 @@ idpf_ptp_get_tstamp_value(struct idpf_vport *vport,
/**
* idpf_ptp_get_tx_tstamp_async_handler - Async callback for getting Tx tstamps
* @adapter: Driver specific private structure
* @xn: transaction for message
* @ctlq_msg: received message
* @ctx: adapter pointer
* @mem: address and size of the response
* @status: return value of the request
*
* Read the tstamps Tx tstamp values from a received message and put them
* directly to the skb. The number of timestamps to read is specified by
@ -546,22 +537,26 @@ idpf_ptp_get_tstamp_value(struct idpf_vport *vport,
*
* Return: 0 on success, -errno otherwise.
*/
static int
idpf_ptp_get_tx_tstamp_async_handler(struct idpf_adapter *adapter,
struct idpf_vc_xn *xn,
const struct idpf_ctlq_msg *ctlq_msg)
static void
idpf_ptp_get_tx_tstamp_async_handler(void *ctx, struct kvec *mem, int status)
{
struct virtchnl2_ptp_get_vport_tx_tstamp_latches *recv_tx_tstamp_msg;
struct idpf_ptp_vport_tx_tstamp_caps *tx_tstamp_caps;
struct virtchnl2_ptp_tx_tstamp_latch tstamp_latch;
struct idpf_ptp_tx_tstamp *tx_tstamp, *tmp;
struct idpf_vport *tstamp_vport = NULL;
struct idpf_adapter *adapter = ctx;
struct list_head *head;
u16 num_latches;
u32 vport_id;
int err = 0;
recv_tx_tstamp_msg = ctlq_msg->ctx.indirect.payload->va;
if (status)
return;
recv_tx_tstamp_msg = mem->iov_base;
if (mem->iov_len < sizeof(*recv_tx_tstamp_msg))
return;
vport_id = le32_to_cpu(recv_tx_tstamp_msg->vport_id);
idpf_for_each_vport(adapter, vport) {
@ -575,10 +570,13 @@ idpf_ptp_get_tx_tstamp_async_handler(struct idpf_adapter *adapter,
}
if (!tstamp_vport || !tstamp_vport->tx_tstamp_caps)
return -EINVAL;
return;
tx_tstamp_caps = tstamp_vport->tx_tstamp_caps;
num_latches = le16_to_cpu(recv_tx_tstamp_msg->num_latches);
if (mem->iov_len < struct_size(recv_tx_tstamp_msg, tstamp_latches,
num_latches))
return;
spin_lock_bh(&tx_tstamp_caps->latches_lock);
head = &tx_tstamp_caps->latches_in_use;
@ -589,13 +587,13 @@ idpf_ptp_get_tx_tstamp_async_handler(struct idpf_adapter *adapter,
if (!tstamp_latch.valid)
continue;
if (list_empty(head)) {
err = -ENOBUFS;
if (list_empty(head))
goto unlock;
}
list_for_each_entry_safe(tx_tstamp, tmp, head, list_member) {
if (tstamp_latch.index == tx_tstamp->idx) {
int err;
list_del(&tx_tstamp->list_member);
err = idpf_ptp_get_tstamp_value(tstamp_vport,
&tstamp_latch,
@ -610,8 +608,6 @@ idpf_ptp_get_tx_tstamp_async_handler(struct idpf_adapter *adapter,
unlock:
spin_unlock_bh(&tx_tstamp_caps->latches_lock);
return err;
}
/**
@ -627,15 +623,15 @@ int idpf_ptp_get_tx_tstamp(struct idpf_vport *vport)
{
struct virtchnl2_ptp_get_vport_tx_tstamp_latches *send_tx_tstamp_msg;
struct idpf_ptp_vport_tx_tstamp_caps *tx_tstamp_caps;
struct idpf_vc_xn_params xn_params = {
.vc_op = VIRTCHNL2_OP_PTP_GET_VPORT_TX_TSTAMP,
struct libie_ctlq_xn_send_params xn_params = {
.chnl_opcode = VIRTCHNL2_OP_PTP_GET_VPORT_TX_TSTAMP,
.timeout_ms = IDPF_VC_XN_DEFAULT_TIMEOUT_MSEC,
.async = true,
.async_handler = idpf_ptp_get_tx_tstamp_async_handler,
.resp_cb = idpf_ptp_get_tx_tstamp_async_handler,
.send_ctx = vport->adapter,
};
struct idpf_ptp_tx_tstamp *ptp_tx_tstamp;
int reply_sz, size, msg_size;
struct list_head *head;
int size, msg_size;
bool state_upd;
u16 id = 0;
@ -668,11 +664,7 @@ int idpf_ptp_get_tx_tstamp(struct idpf_vport *vport)
msg_size = struct_size(send_tx_tstamp_msg, tstamp_latches, id);
send_tx_tstamp_msg->vport_id = cpu_to_le32(vport->vport_id);
send_tx_tstamp_msg->num_latches = cpu_to_le16(id);
xn_params.send_buf.iov_base = send_tx_tstamp_msg;
xn_params.send_buf.iov_len = msg_size;
reply_sz = idpf_vc_xn_exec(vport->adapter, &xn_params);
kfree(send_tx_tstamp_msg);
return min(reply_sz, 0);
return idpf_send_mb_msg_kfree(vport->adapter, &xn_params,
send_tx_tstamp_msg, msg_size);
}