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drm/rockchip: vop: add rk3066 vop support

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Change-Id: Icdb826c3f7b9e5dc36fd27dfa6bc401c026057ec
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
This commit is contained in:
Mark Yao 2017-11-07 10:26:51 +08:00 committed by Tao Huang
parent 32a54e3a26
commit de862e8bbc
3 changed files with 162 additions and 2 deletions
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1
Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
View File

@ -7,6 +7,7 @@ buffer to an external LCD interface.
Required properties:
- compatible: value should be one of the following
"rockchip,rk3036-vop";
"rockchip,rk3066-vop";
"rockchip,rk3126-vop";
"rockchip,rk3288-vop";
"rockchip,rk3368-vop";

112
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@ -684,7 +684,7 @@ static const struct vop_data rk3328_vop = {
.win_size = ARRAY_SIZE(rk3328_vop_win_data),
};
static const struct vop_scl_regs rk3066_win_scl = {
static const struct vop_scl_regs rk3036_win_scl = {
.scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
.scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
.scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
@ -692,7 +692,7 @@ static const struct vop_scl_regs rk3066_win_scl = {
};
static const struct vop_win_phy rk3036_win0_data = {
.scl = &rk3066_win_scl,
.scl = &rk3036_win_scl,
.data_formats = formats_win_full,
.nformats = ARRAY_SIZE(formats_win_full),
.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
@ -771,6 +771,112 @@ static const struct vop_data rk3036_vop = {
.win_size = ARRAY_SIZE(rk3036_vop_win_data),
};
static const struct vop_scl_regs rk3066_win_scl = {
.scale_yrgb_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
.scale_yrgb_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
.scale_cbcr_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
.scale_cbcr_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
};
static const struct vop_win_phy rk3066_win0_data = {
.scl = &rk3066_win_scl,
.data_formats = formats_win_full,
.nformats = ARRAY_SIZE(formats_win_full),
.enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 0),
.format = VOP_REG(RK3066_SYS_CTRL0, 0x7, 4),
.rb_swap = VOP_REG(RK3066_SYS_CTRL0, 0x1, 19),
.act_info = VOP_REG(RK3066_WIN0_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3066_WIN0_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3066_WIN0_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3066_WIN0_YRGB_MST0, 0xffffffff, 0),
.uv_mst = VOP_REG(RK3066_WIN0_CBR_MST0, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3066_WIN0_VIR, 0xffff, 0),
.uv_vir = VOP_REG(RK3066_WIN0_VIR, 0x1fff, 16),
.alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 21),
.alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 0)
};
static const struct vop_win_phy rk3066_win1_data = {
.scl = &rk3066_win_scl,
.data_formats = formats_win_full,
.nformats = ARRAY_SIZE(formats_win_full),
.enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 1),
.format = VOP_REG(RK3066_SYS_CTRL0, 0x7, 7),
.rb_swap = VOP_REG(RK3066_SYS_CTRL0, 0x1, 23),
.act_info = VOP_REG(RK3066_WIN1_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3066_WIN1_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3066_WIN1_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3066_WIN1_YRGB_MST, 0xffffffff, 0),
.uv_mst = VOP_REG(RK3066_WIN1_CBR_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3066_WIN1_VIR, 0xffff, 0),
.uv_vir = VOP_REG(RK3066_WIN1_VIR, 0x1fff, 16),
.alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 22),
.alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 1)
};
static const struct vop_win_phy rk3066_win2_data = {
.data_formats = formats_win_lite,
.nformats = ARRAY_SIZE(formats_win_lite),
.enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 2),
.format = VOP_REG(RK3066_SYS_CTRL0, 0x7, 10),
.rb_swap = VOP_REG(RK3066_SYS_CTRL0, 0x1, 27),
.dsp_info = VOP_REG(RK3066_WIN2_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3066_WIN2_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3066_WIN2_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3066_WIN2_VIR, 0xffff, 0),
.alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 23),
.alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 2)
};
static const struct vop_win_data rk3066_vop_win_data[] = {
{ .base = 0x00, .phy = &rk3066_win0_data,
.type = DRM_PLANE_TYPE_PRIMARY },
{ .base = 0x00, .phy = &rk3066_win1_data,
.type = DRM_PLANE_TYPE_OVERLAY },
{ .base = 0x00, .phy = &rk3066_win2_data,
.type = DRM_PLANE_TYPE_CURSOR },
};
static const int rk3066_vop_intrs[] = {
0,
FS_INTR,
LINE_FLAG_INTR,
BUS_ERROR_INTR,
};
static const struct vop_intr rk3066_intr = {
.intrs = rk3066_vop_intrs,
.nintrs = ARRAY_SIZE(rk3066_vop_intrs),
.line_flag_num[0] = VOP_REG(RK3066_INT_STATUS, 0xfff, 12),
.status = VOP_REG(RK3066_INT_STATUS, 0xf, 0),
.enable = VOP_REG(RK3066_INT_STATUS, 0xf, 4),
.clear = VOP_REG(RK3066_INT_STATUS, 0xf, 8),
};
static const struct vop_ctrl rk3066_ctrl_data = {
.standby = VOP_REG(RK3066_SYS_CTRL0, 0x1, 1),
.out_mode = VOP_REG(RK3066_DSP_CTRL0, 0xf, 0),
.dsp_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 24),
.dclk_pol = VOP_REG(RK3066_DSP_CTRL0, 0x1, 7),
.pin_pol = VOP_REG(RK3066_DSP_CTRL0, 0x7, 4),
.dsp_layer_sel = VOP_REG(RK3066_DSP_CTRL0, 0x1, 8),
.htotal_pw = VOP_REG(RK3066_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3066_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3066_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3066_DSP_VACT_ST_END, 0x1fff1fff, 0),
.cfg_done = VOP_REG(RK3066_REG_CFG_DONE, 0x1, 0),
};
static const struct vop_data rk3066_vop = {
.version = VOP_VERSION(2, 1),
.max_input = {1920, 4096},
.max_output = {1920, 1080},
.ctrl = &rk3066_ctrl_data,
.intr = &rk3066_intr,
.win = rk3066_vop_win_data,
.win_size = ARRAY_SIZE(rk3066_vop_win_data),
};
static const int rk3366_vop_lit_intrs[] = {
FS_INTR,
FS_NEW_INTR,
@ -931,6 +1037,8 @@ static const struct vop_data rk3126_vop = {
static const struct of_device_id vop_driver_dt_match[] = {
{ .compatible = "rockchip,rk3036-vop",
.data = &rk3036_vop },
{ .compatible = "rockchip,rk3066-vop",
.data = &rk3066_vop },
{ .compatible = "rockchip,rk3126-vop",
.data = &rk3126_vop },
{ .compatible = "rockchip,rk3288-vop",

51
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
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@ -883,6 +883,57 @@
#define RK3036_HWC_LUT_ADDR 0x800
/* rk3036 register definition end */
#define RK3066_SYS_CTRL0 0x00
#define RK3066_SYS_CTRL1 0x04
#define RK3066_DSP_CTRL0 0x08
#define RK3066_DSP_CTRL1 0x0c
#define RK3066_INT_STATUS 0x10
#define RK3066_MCU_CTRL 0x14
#define RK3066_BLEND_CTRL 0x18
#define RK3066_WIN0_COLOR_KEY_CTRL 0x1c
#define RK3066_WIN1_COLOR_KEY_CTRL 0x20
#define RK3066_WIN2_COLOR_KEY_CTRL 0x24
#define RK3066_WIN0_YRGB_MST0 0x28
#define RK3066_WIN0_CBR_MST0 0x2c
#define RK3066_WIN0_YRGB_MST1 0x30
#define RK3066_WIN0_CBR_MST1 0x34
#define RK3066_WIN0_VIR 0x38
#define RK3066_WIN0_ACT_INFO 0x3c
#define RK3066_WIN0_DSP_INFO 0x40
#define RK3066_WIN0_DSP_ST 0x44
#define RK3066_WIN0_SCL_FACTOR_YRGB 0x48
#define RK3066_WIN0_SCL_FACTOR_CBR 0x4c
#define RK3066_WIN0_SCL_OFFSET 0x50
#define RK3066_WIN1_YRGB_MST 0x54
#define RK3066_WIN1_CBR_MST 0x58
#define RK3066_WIN1_VIR 0x5c
#define RK3066_WIN1_ACT_INFO 0x60
#define RK3066_WIN1_DSP_INFO 0x64
#define RK3066_WIN1_DSP_ST 0x68
#define RK3066_WIN1_SCL_FACTOR_YRGB 0x6c
#define RK3066_WIN1_SCL_FACTOR_CBR 0x70
#define RK3066_WIN1_SCL_OFFSET 0x74
#define RK3066_WIN2_MST 0x78
#define RK3066_WIN2_VIR 0x7c
#define RK3066_WIN2_DSP_INFO 0x80
#define RK3066_WIN2_DSP_ST 0x84
#define RK3066_HWC_MST 0x88
#define RK3066_HWC_DSP_ST 0x8c
#define RK3066_HWC_COLOR_LUT0 0x90
#define RK3066_HWC_COLOR_LUT1 0x94
#define RK3066_HWC_COLOR_LUT2 0x98
#define RK3066_DSP_HTOTAL_HS_END 0x9c
#define RK3066_DSP_HACT_ST_END 0xa0
#define RK3066_DSP_VTOTAL_VS_END 0xa4
#define RK3066_DSP_VACT_ST_END 0xa8
#define RK3066_DSP_VS_ST_END_F1 0xac
#define RK3066_DSP_VACT_ST_END_F1 0xb0
#define RK3066_REG_CFG_DONE 0xc0
#define RK3066_MCU_BYPASS_WPORT 0x100
#define RK3066_MCU_BYPASS_RPORT 0x200
#define RK3066_WIN2_LUT_ADDR 0x400
#define RK3066_DSP_LUT_ADDR 0x800
/* rk3366 register definition */
#define RK3366_LIT_REG_CFG_DONE 0x00000
#define RK3366_LIT_VERSION 0x00004