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Merge "msm: geni: common: Add common driver for pineapple"
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357
include/linux/qcom-geni-se-common.h
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357
include/linux/qcom-geni-se-common.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _LINUX_QCOM_GENI_SE_COMMON
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#define _LINUX_QCOM_GENI_SE_COMMON
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#include <linux/clk.h>
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#include <linux/dma-direction.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#ifdef CONFIG_ARM64
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#define GENI_SE_DMA_PTR_L(ptr) ((u32)ptr)
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#define GENI_SE_DMA_PTR_H(ptr) ((u32)(ptr >> 32))
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#else
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#define GENI_SE_DMA_PTR_L(ptr) ((u32)ptr)
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#define GENI_SE_DMA_PTR_H(ptr) 0
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#endif
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#define GENI_SE_ERR(log_ctx, print, dev, x...) do { \
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ipc_log_string(log_ctx, x); \
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if (print) { \
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if (dev) \
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dev_err((dev), x); \
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else \
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pr_err(x); \
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} \
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} while (0)
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#define GENI_SE_DBG(log_ctx, print, dev, x...) do { \
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ipc_log_string(log_ctx, x); \
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if (print) { \
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if (dev) \
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dev_dbg((dev), x); \
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else \
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pr_debug(x); \
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} \
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} while (0)
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#define SE_DMA_DEBUG_REG0 (0xE40)
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#define SE_DMA_TX_PTR_L (0xC30)
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#define SE_DMA_TX_PTR_H (0xC34)
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#define SE_DMA_TX_LEN (0xC3C)
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#define SE_DMA_TX_IRQ_EN (0xC48)
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#define SE_DMA_TX_LEN_IN (0xC54)
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#define SE_DMA_RX_PTR_L (0xD30)
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#define SE_DMA_RX_PTR_H (0xD34)
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#define SE_DMA_RX_ATTR (0xD38)
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#define SE_DMA_RX_LEN (0xD3C)
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#define SE_DMA_RX_IRQ_EN (0xD48)
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#define SE_DMA_RX_LEN_IN (0xD54)
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#define SE_DMA_TX_IRQ_EN_SET (0xC4C)
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#define SE_DMA_TX_IRQ_EN_CLR (0xC50)
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#define SE_DMA_RX_IRQ_EN_SET (0xD4C)
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#define SE_DMA_RX_IRQ_EN_CLR (0xD50)
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#define TX_GENI_CANCEL_IRQ (BIT(14))
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/* DMA DEBUG Register fields */
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#define DMA_TX_ACTIVE (BIT(0))
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#define DMA_RX_ACTIVE (BIT(1))
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#define DMA_TX_STATE (GENMASK(7, 4))
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#define DMA_RX_STATE (GENMASK(11, 8))
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/* SE_IRQ_EN fields */
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#define DMA_RX_IRQ_EN (BIT(0))
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#define DMA_TX_IRQ_EN (BIT(1))
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#define GENI_M_IRQ_EN (BIT(2))
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#define GENI_S_IRQ_EN (BIT(3))
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#define GENI_FW_S_REVISION_RO (0x6C)
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#define FW_REV_VERSION_MSK (GENMASK(7, 0))
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#define GSI_TX_PACK_EN (BIT(0))
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#define GSI_RX_PACK_EN (BIT(1))
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#define GSI_PRESERVE_PACK (BIT(2))
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#define HW_VER_MAJOR_MASK GENMASK(31, 28)
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#define HW_VER_MAJOR_SHFT 28
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#define HW_VER_MINOR_MASK GENMASK(27, 16)
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#define HW_VER_MINOR_SHFT 16
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#define HW_VER_STEP_MASK GENMASK(15, 0)
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static inline int geni_se_common_resources_init(struct geni_se *se, u32 geni_to_core,
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u32 cpu_to_geni, u32 geni_to_ddr)
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{
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int ret;
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ret = geni_icc_get(se, "qup-memory");
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if (ret)
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return ret;
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se->icc_paths[GENI_TO_CORE].avg_bw = geni_to_core;
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se->icc_paths[CPU_TO_GENI].avg_bw = cpu_to_geni;
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se->icc_paths[GENI_TO_DDR].avg_bw = geni_to_ddr;
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return ret;
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}
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static inline int geni_se_common_get_proto(void __iomem *base)
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{
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int proto;
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proto = ((readl_relaxed(base + GENI_FW_REVISION_RO)
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& FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT);
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return proto;
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}
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/**
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* geni_se_common_get_m_fw - Read the Firmware ver for the Main sequencer engine
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* @base: Base address of the serial engine's register block.
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*
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* Return: Firmware version for the Main sequencer engine
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*/
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static inline int geni_se_common_get_m_fw(void __iomem *base)
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{
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int fw_ver_m;
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fw_ver_m = ((readl_relaxed(base + GENI_FW_REVISION_RO)
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& FW_REV_VERSION_MSK));
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return fw_ver_m;
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}
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/**
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* geni_se_common_get_s_fw() - Read the Firmware ver for the Secondry sequencer engine
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* @base: Base address of the serial engine's register block.
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*
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* Return: Firmware version for the Secondry sequencer engine
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*/
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static inline int geni_se_common_get_s_fw(void __iomem *base)
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{
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int fw_ver_s;
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fw_ver_s = ((readl_relaxed(base + GENI_FW_S_REVISION_RO)
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& FW_REV_VERSION_MSK));
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return fw_ver_s;
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}
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/**
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* geni_se_common_clks_off - Disabling SE clks and common clks
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* @se_clk: Pointer to the SE-CLk.
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* @m_ahb_clk: Pointer to the SE common m_ahb_clk.
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* @s_ahb_clk: Pointer to the SE common s_ahb_clk.
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*/
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static inline void geni_se_common_clks_off(struct clk *se_clk, struct clk *m_ahb_clk,
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struct clk *s_ahb_clk)
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{
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clk_disable_unprepare(se_clk);
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clk_disable_unprepare(m_ahb_clk);
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clk_disable_unprepare(s_ahb_clk);
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}
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/**
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* geni_se_common_clks_on - enabling SE clks and common clks
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* @se_clk: Pointer to the SE-CLk.
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* @m_ahb_clk: Pointer to the SE common m_ahb_clk.
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* @s_ahb_clk: Pointer to the SE common s_ahb_clk.
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*/
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static inline int geni_se_common_clks_on(struct clk *se_clk, struct clk *m_ahb_clk,
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struct clk *s_ahb_clk)
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{
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int ret;
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ret = clk_prepare_enable(m_ahb_clk);
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if (ret)
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goto clks_on_err1;
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ret = clk_prepare_enable(s_ahb_clk);
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if (ret)
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goto clks_on_err2;
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ret = clk_prepare_enable(se_clk);
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if (ret)
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goto clks_on_err3;
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return 0;
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clks_on_err3:
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clk_disable_unprepare(s_ahb_clk);
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clks_on_err2:
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clk_disable_unprepare(m_ahb_clk);
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clks_on_err1:
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return ret;
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}
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/**
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* geni_write_reg() - Helper function to write into a GENI register
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* @value: Value to be written into the register.
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* @base: Base address of the serial engine's register block.
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* @offset: Offset within the serial engine's register block.
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*/
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static inline void geni_write_reg(unsigned int value, void __iomem *base, int offset)
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{
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return writel_relaxed(value, (base + offset));
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}
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/**
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* geni_read_reg() - Helper function to read from a GENI register
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* @base: Base address of the serial engine's register block.
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* @offset: Offset within the serial engine's register block.
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*
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* Return: Return the contents of the register.
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*/
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static inline unsigned int geni_read_reg(void __iomem *base, int offset)
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{
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return readl_relaxed(base + offset);
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}
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/**
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* geni_se_common_iommu_map_buf() - Map a single buffer into QUPv3 context bank
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* @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
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* @iova: Pointer in which the mapped virtual address is stored.
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* @buf: Address of the buffer that needs to be mapped.
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* @size: Size of the buffer.
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* @dir: Direction of the DMA transfer.
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*
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* This function is used to map an already allocated buffer into the
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* QUPv3 context bank device space.
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*
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* Return: 0 on success, standard Linux error codes on failure/error.
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*/
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static inline int geni_se_common_iommu_map_buf(struct device *wrapper_dev, dma_addr_t *iova,
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void *buf, size_t size, enum dma_data_direction dir)
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{
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if (!wrapper_dev)
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return -EINVAL;
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*iova = dma_map_single(wrapper_dev, buf, size, dir);
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if (dma_mapping_error(wrapper_dev, *iova))
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return -EIO;
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return 0;
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}
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/**
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* geni_se_common_iommu_unmap_buf() - Unmap a single buffer from QUPv3 context bank
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* @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
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* @iova: Pointer in which the mapped virtual address is stored.
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* @size: Size of the buffer.
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* @dir: Direction of the DMA transfer.
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*
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* This function is used to unmap an already mapped buffer from the
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* QUPv3 context bank device space.
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*
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* Return: 0 on success, standard Linux error codes on failure/error.
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*/
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static inline int geni_se_common_iommu_unmap_buf(struct device *wrapper_dev, dma_addr_t *iova,
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size_t size, enum dma_data_direction dir)
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{
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if (!dma_mapping_error(wrapper_dev, *iova))
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dma_unmap_single(wrapper_dev, *iova, size, dir);
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return 0;
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}
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/**
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* geni_se_common_iommu_alloc_buf() - Allocate & map a single buffer into QUPv3
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* context bank
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* @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
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* @iova: Pointer in which the mapped virtual address is stored.
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* @size: Size of the buffer.
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*
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* This function is used to allocate a buffer and map it into the
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* QUPv3 context bank device space.
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*
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* Return: address of the buffer on success, NULL or ERR_PTR on
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* failure/error.
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*/
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static inline void *geni_se_common_iommu_alloc_buf(struct device *wrapper_dev, dma_addr_t *iova,
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size_t size)
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{
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void *buf = NULL;
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if (!wrapper_dev || !iova || !size)
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return ERR_PTR(-EINVAL);
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*iova = DMA_MAPPING_ERROR;
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buf = dma_alloc_coherent(wrapper_dev, size, iova, GFP_KERNEL);
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return buf;
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}
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/**
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* geni_se_common_iommu_free_buf() - Unmap & free a single buffer from QUPv3
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* context bank
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* @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
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* @iova: Pointer in which the mapped virtual address is stored.
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* @buf: Address of the buffer.
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* @size: Size of the buffer.
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*
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* This function is used to unmap and free a buffer from the
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* QUPv3 context bank device space.
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*
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* Return: 0 on success, standard Linux error codes on failure/error.
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*/
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static inline int geni_se_common_iommu_free_buf(struct device *wrapper_dev, dma_addr_t *iova,
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void *buf, size_t size)
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{
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if (!wrapper_dev || !iova || !buf || !size)
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return -EINVAL;
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dma_free_coherent(wrapper_dev, size, buf, *iova);
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return 0;
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}
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/**
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* geni_se_common_rx_dma_start() - Prepare Serial Engine registers for RX DMA
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transfers.
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* @base: Base address of the SE register block.
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* @rx_len: Length of the RX buffer.
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* @rx_dma: Pointer to store the mapped DMA address.
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*
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* This function is used to prepare the Serial Engine registers for DMA RX.
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*
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* Return: None.
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*/
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static inline void geni_se_common_rx_dma_start(void __iomem *base, int rx_len, dma_addr_t *rx_dma)
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{
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if (!*rx_dma || !base || !rx_len)
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return;
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geni_write_reg(7, base, SE_DMA_RX_IRQ_EN_SET);
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geni_write_reg(GENI_SE_DMA_PTR_L(*rx_dma), base, SE_DMA_RX_PTR_L);
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geni_write_reg(GENI_SE_DMA_PTR_H(*rx_dma), base, SE_DMA_RX_PTR_H);
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/* RX does not have EOT bit */
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geni_write_reg(0, base, SE_DMA_RX_ATTR);
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/* Ensure that above register writes went through */
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mb();
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geni_write_reg(rx_len, base, SE_DMA_RX_LEN);
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}
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/**
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* geni_se_common_get_major_minor_num() - Split qup hw_version into
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major, minor and step.
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* @hw_version: HW version of the qup
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* @major: Buffer for Major Version field.
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* @minor: Buffer for Minor Version field.
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* @step: Buffer for Step Version field.
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*
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* Return: None
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*/
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static inline void geni_se_common_get_major_minor_num(u32 hw_version,
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unsigned int *major, unsigned int *minor, unsigned int *step)
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{
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*major = (hw_version & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT;
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*minor = (hw_version & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT;
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*step = hw_version & HW_VER_STEP_MASK;
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}
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#endif
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