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drm/msm/adreno: write reserved UBWC-related bits

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On the latest A8xx Adreno chips several of the bits in the UBWC-related
registers are now hardwired to 1. Currently the driver doesn't write
them because there is no side-effect. In the preparation for the
refactoring in the next patch, write '1' to those bits anyway.

Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/726504/
Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-15-72f2749bc807@oss.qualcomm.com
This commit is contained in:
Dmitry Baryshkov 2026-05-20 17:51:22 +03:00
parent 86ec9084a2
commit ddbcc87500
1 changed files with 2 additions and 0 deletions
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2
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
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@ -288,6 +288,8 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu)
switch (ubwc_version) {
case UBWC_6_0:
yuvnotcomptofc = true;
amsbc = true;
rgb565_predicator = true;
break;
case UBWC_5_0:
amsbc = true;