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drm/amdgpu: move suballoc defines into own header
Just some code cleanup, while at it remove outdated comment. No functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König
Alex Deucher
parent
4d7c25208c
commit
ddb1149aa2
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@ -114,6 +114,7 @@
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#include "amdgpu_userq.h"
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#include "amdgpu_eviction_fence.h"
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#include "amdgpu_ip.h"
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#include "amdgpu_sa.h"
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#if defined(CONFIG_DRM_AMD_ISP)
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#include "amdgpu_isp.h"
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#endif
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@ -387,37 +388,6 @@ struct amdgpu_clock {
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uint32_t max_pixel_clock;
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};
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/* sub-allocation manager, it has to be protected by another lock.
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* By conception this is an helper for other part of the driver
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* like the indirect buffer or semaphore, which both have their
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* locking.
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*
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* Principe is simple, we keep a list of sub allocation in offset
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* order (first entry has offset == 0, last entry has the highest
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* offset).
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*
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* When allocating new object we first check if there is room at
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* the end total_size - (last_object_offset + last_object_size) >=
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* alloc_size. If so we allocate new object there.
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*
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* When there is not enough room at the end, we start waiting for
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* each sub object until we reach object_offset+object_size >=
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* alloc_size, this object then become the sub object we return.
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*
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* Alignment can't be bigger than page size.
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*
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* Hole are not considered for allocation to keep things simple.
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* Assumption is that there won't be hole (all object on same
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* alignment).
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*/
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struct amdgpu_sa_manager {
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struct drm_suballoc_manager base;
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struct amdgpu_bo *bo;
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uint64_t gpu_addr;
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void *cpu_ptr;
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};
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/*
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* IRQS.
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*/
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@ -312,46 +312,6 @@ uint32_t amdgpu_bo_mem_stats_placement(struct amdgpu_bo *bo);
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uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
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uint32_t domain);
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/*
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* sub allocation
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*/
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static inline struct amdgpu_sa_manager *
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to_amdgpu_sa_manager(struct drm_suballoc_manager *manager)
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{
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return container_of(manager, struct amdgpu_sa_manager, base);
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}
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static inline uint64_t amdgpu_sa_bo_gpu_addr(struct drm_suballoc *sa_bo)
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{
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return to_amdgpu_sa_manager(sa_bo->manager)->gpu_addr +
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drm_suballoc_soffset(sa_bo);
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}
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static inline void *amdgpu_sa_bo_cpu_addr(struct drm_suballoc *sa_bo)
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{
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return to_amdgpu_sa_manager(sa_bo->manager)->cpu_ptr +
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drm_suballoc_soffset(sa_bo);
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}
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int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager,
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unsigned size, u32 align, u32 domain);
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void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager);
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int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager);
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int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
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struct drm_suballoc **sa_bo,
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unsigned int size);
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void amdgpu_sa_bo_free(struct drm_suballoc **sa_bo,
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struct dma_fence *fence);
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#if defined(CONFIG_DEBUG_FS)
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void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
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struct seq_file *m);
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u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m);
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#endif
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void amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
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bool amdgpu_bo_support_uswc(u64 bo_flags);
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77
drivers/gpu/drm/amd/amdgpu/amdgpu_sa.h
Normal file
77
drivers/gpu/drm/amd/amdgpu/amdgpu_sa.h
Normal file
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@ -0,0 +1,77 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2026 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef AMDGPU_SA_H_
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#define AMDGPU_SA_H_
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#include <drm/drm_suballoc.h>
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struct amdgpu_device;
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struct amdgpu_bo;
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struct amdgpu_sa_manager {
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struct drm_suballoc_manager base;
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struct amdgpu_bo *bo;
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uint64_t gpu_addr;
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void *cpu_ptr;
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};
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static inline struct amdgpu_sa_manager *
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to_amdgpu_sa_manager(struct drm_suballoc_manager *manager)
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{
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return container_of(manager, struct amdgpu_sa_manager, base);
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}
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static inline uint64_t amdgpu_sa_bo_gpu_addr(struct drm_suballoc *sa_bo)
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{
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return to_amdgpu_sa_manager(sa_bo->manager)->gpu_addr +
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drm_suballoc_soffset(sa_bo);
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}
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static inline void *amdgpu_sa_bo_cpu_addr(struct drm_suballoc *sa_bo)
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{
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return to_amdgpu_sa_manager(sa_bo->manager)->cpu_ptr +
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drm_suballoc_soffset(sa_bo);
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}
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int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager,
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unsigned size, u32 align, u32 domain);
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void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager);
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int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager);
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int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
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struct drm_suballoc **sa_bo,
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unsigned int size);
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void amdgpu_sa_bo_free(struct drm_suballoc **sa_bo,
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struct dma_fence *fence);
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#if defined(CONFIG_DEBUG_FS)
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void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
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struct seq_file *m);
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u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m);
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#endif
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void amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
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#endif
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