From 00abee2b18342d6c2f6f37225682fa7ca0d33142 Mon Sep 17 00:00:00 2001 From: Detlev Casanova Date: Tue, 8 Jul 2025 11:50:10 -0400 Subject: [PATCH 01/29] arm64: dts: rockchip: Add UFS support on the ROCK 4D This device supports removable UFS chips, add support for it. Signed-off-by: Detlev Casanova Link: https://lore.kernel.org/r/20250708155010.401446-1-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts index 0388d72076bf..22ffa15abc9e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts @@ -745,6 +745,10 @@ &uart0 { status = "okay"; }; +&ufshc { + status = "okay"; +}; + &usb_drd1_dwc3 { dr_mode = "host"; status = "okay"; From 06b29cb849bc0437edd68373a1e8152f0bcd30e7 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sun, 6 Jul 2025 19:38:24 +0800 Subject: [PATCH 02/29] arm64: dts: rockchip: Enable mipi dsi on rk3568-evb1-v10 Enable the w552793baa 1080x1920 dsi panel on rk3568 evb1. Signed-off-by: Andy Yan Link: https://lore.kernel.org/r/20250706113831.330799-1-andyshrk@163.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3568-evb1-v10.dts | 66 ++++++++++++++++++- 1 file changed, 64 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index b073a4d03e4f..b01f952b640e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -22,6 +22,15 @@ aliases { mmc1 = &sdhci; }; + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <20 220>; + default-brightness-level = <100>; + num-interpolated-steps = <200>; + power-supply = <&vcc3v3_sys>; + pwms = <&pwm4 0 25000 0>; + }; + chosen: chosen { stdout-path = "serial2:1500000n8"; }; @@ -184,6 +193,47 @@ &cpu3 { cpu-supply = <&vdd_cpu>; }; +&dsi0 { + clock-master; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "wanchanglong,w552793baa", "raydium,rm67200"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; + vdd-supply = <&vcc3v3_lcd0_n>; + vsn-supply = <&vcc5v0_sys>; + vsp-supply = <&vcc5v0_sys>; + + port { + panel_in_dsi: endpoint { + remote-endpoint = <&dsi0_out_panel>; + }; + }; + }; + +}; + +&dsi0_in { + dsi0_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dsi0>; + }; +}; + +&dsi0_out { + dsi0_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; +}; + +&dsi_dphy0 { + status = "okay"; +}; + &gmac0 { assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; @@ -581,6 +631,10 @@ &pmu_io_domains { status = "okay"; }; +&pwm4 { + status = "okay"; +}; + &saradc { vref-supply = <&vcca_1v8>; status = "okay"; @@ -672,8 +726,9 @@ &usb2phy1_otg { }; &vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + assigned-clocks = <&cru DCLK_VOP0>, <&cru PLL_VPLL>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&xin24m>, <&cru PLL_VPLL>; + assigned-clock-rates = <0>, <132000000>, <132000000>; status = "okay"; }; @@ -687,3 +742,10 @@ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { remote-endpoint = <&hdmi_in_vp0>; }; }; + +&vp1 { + vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg = ; + remote-endpoint = <&dsi0_in_vp1>; + }; +}; From cd803da7c033e376a66793a43ee98e136bc6cc25 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Fri, 4 Jul 2025 19:31:59 +0200 Subject: [PATCH 03/29] arm64: dts: rockchip: fix PHY handling for ROCK 4D Old revisions of the ROCK 4D board have a dedicated crystal to supply the RTL8211F PHY's 25MHz clock input. At least some newer revisions instead use REFCLKO25M_GMAC0_OUT. The DT already has this half-prepared, but there are some issues: 1. The DT relies on auto-selecting the right PHY driver, which requires that it works good enough to read the ID registers. This does not work without the clock, which is handled by the PHY driver. By updating the compatible to contain the RTL8211F IDs, so that the operating system can choose the right PHY driver without relying on a pre-powered PHY. 2. Despite the name REFCLKO25M_GMAC0_OUT could also provide a different frequency, so ensure it is explicitly set to 25 MHz as expected by the PHY. 3. While at it switch from deprecated "enable-gpio" to standard "enable-gpios". Fixes: a0fb7eca9c09 ("arm64: dts: rockchip: Add Radxa ROCK 4D device tree") Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20250704-rk3576-rock4d-phy-handling-fixes-v1-1-1d64130c4139@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts index 22ffa15abc9e..62712c90c83d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts @@ -645,14 +645,16 @@ hym8563: rtc@51 { &mdio0 { rgmii_phy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id001c.c916"; reg = <0x1>; clocks = <&cru REFCLKO25M_GMAC0_OUT>; + assigned-clocks = <&cru REFCLKO25M_GMAC0_OUT>; + assigned-clock-rates = <25000000>; pinctrl-names = "default"; pinctrl-0 = <&rtl8211f_rst>; reset-assert-us = <20000>; reset-deassert-us = <100000>; - reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; }; }; From e2fe8ad8f1e62c424b8b73cc89d1bc53d19c41b2 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Fri, 4 Jul 2025 19:14:14 +0200 Subject: [PATCH 04/29] arm64: dts: rockchip: Enable HDMI receiver on RK3588 EVB1 Enable HDMI input port of the RK3588 EVB1. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20250704-rk3588-evb1-hdmi-rx-v1-1-248315c36ccd@kernel.org Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index 8e912da299a2..ff1ba5ed56ef 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -391,6 +391,17 @@ hdmi1_out_con: endpoint { }; }; +&hdmi_receiver_cma { + status = "okay"; +}; + +&hdmi_receiver { + hpd-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; + pinctrl-names = "default"; + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -582,6 +593,12 @@ rtl8211f_rst: rtl8211f-rst { }; + hdmirx { + hdmirx_hpd: hdmirx-5v-detection { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; From 9a625a284bfdb902f27f2949063731d189adda3c Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Mon, 30 Jun 2025 17:36:33 +0200 Subject: [PATCH 05/29] arm64: dts: rockchip: adjust dcin regulator on ROCK 4D The ROCK 4D's actual DC input is 5V, and the schematic names it as being 5V as well. Rename the regulator, and change the voltage it claims to be at. Furthermore, fix vcc_1v1_nldo_s3's vin-supply as coming from vcc_5v0_sys, and not the DCIN, as per the schematic. This makes no functional change; both regulators are always on, and one feeds into the other. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20250630-rock4d-reg-usb-wifi-v1-1-1057f412d98c@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts index 62712c90c83d..ee0822cd4f35 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts @@ -57,13 +57,13 @@ user-led { }; }; - vcc_12v0_dcin: regulator-vcc-12v0-dcin { + vcc_5v0_dcin: regulator-vcc-5v0-dcin { compatible = "regulator-fixed"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-name = "vcc_12v0_dcin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc_5v0_dcin"; }; vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { @@ -166,7 +166,7 @@ vcc_5v0_device: regulator-vcc-5v0-device { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-name = "vcc_5v0_device"; - vin-supply = <&vcc_12v0_dcin>; + vin-supply = <&vcc_5v0_sys>; }; vcc_5v0_host: regulator-vcc-5v0-host { @@ -190,7 +190,7 @@ vcc_5v0_sys: regulator-vcc-5v0-sys { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-name = "vcc_5v0_sys"; - vin-supply = <&vcc_12v0_dcin>; + vin-supply = <&vcc_5v0_dcin>; }; }; From 787595b423d855bfcbf724822fd1e663ad368d08 Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Mon, 30 Jun 2025 17:36:34 +0200 Subject: [PATCH 06/29] arm64: dts: rockchip: complete USB nodes on ROCK 4D The ROCK 4D uses both USB controllers, and both of which in host mode. However, it still names one of the supplies for them "OTG" in the schematic. Fix the "host" supply's input, and add the "otg" supply. Enable the remaining USB PHY nodes, and the first controller node as well. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20250630-rock4d-reg-usb-wifi-v1-2-1057f412d98c@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3576-rock-4d.dts | 41 ++++++++++++++++++- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts index ee0822cd4f35..87bc9004fca1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts @@ -180,7 +180,21 @@ vcc_5v0_host: regulator-vcc-5v0-host { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-name = "vcc5v0_host"; - vin-supply = <&vcc_5v0_device>; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_5v0_otg: regulator-vcc-5v0-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_otg"; + vin-supply = <&vcc_5v0_sys>; }; vcc_5v0_sys: regulator-vcc-5v0-sys { @@ -699,7 +713,11 @@ pcie_reset: pcie-reset { usb { usb_host_pwren: usb-host-pwren { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; }; @@ -738,10 +756,20 @@ &u2phy0 { status = "okay"; }; +&u2phy0_otg { + phy-supply = <&vcc_5v0_otg>; + status = "okay"; +}; + &u2phy1 { status = "okay"; }; +&u2phy1_otg { + phy-supply = <&vcc_5v0_host>; + status = "okay"; +}; + &uart0 { pinctrl-0 = <&uart0m0_xfer>; status = "okay"; @@ -751,6 +779,15 @@ &ufshc { status = "okay"; }; +&usbdp_phy { + status = "okay"; +}; + +&usb_drd0_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + &usb_drd1_dwc3 { dr_mode = "host"; status = "okay"; From eebf59470a76a38d0c43005a34483e1a52a33de0 Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Mon, 30 Jun 2025 17:36:35 +0200 Subject: [PATCH 07/29] arm64: dts: rockchip: theoretically enable Wi-Fi on ROCK 4D The production version of the ROCK 4D appears to sport a AICSEMI AIC8800D80 USB Wi-Fi + BT chipset. This chip does not yet have a mainline driver. Add the necessary rfkill node and wifi regulator node to at least make it show up in lsusb output. The regulator is set as always-on, as like 2 hours deep into debugging why onboard_usb_dev.c wouldn't try enabling the regulator the device needs to actually show up and thus bind to onboard_usb_dev.c, I decided that it's not worth the effort. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20250630-rock4d-reg-usb-wifi-v1-3-1057f412d98c@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3576-rock-4d.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts index 87bc9004fca1..c2683c2a2f04 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts @@ -37,6 +37,14 @@ hdmi_con_in: endpoint { }; }; + rfkill { + compatible = "rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_en_h>; + radio-type = "wlan"; + shutdown-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>; + }; + leds: leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -159,6 +167,19 @@ vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 { vin-supply = <&vcc_5v0_sys>; }; + vcc_3v3_wifi: regulator-vcc-3v3-wifi { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_wifi_pwr>; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_wifi"; + vin-supply = <&vcc_3v3_s3>; + }; + vcc_5v0_device: regulator-vcc-5v0-device { compatible = "regulator-fixed"; regulator-always-on; @@ -720,6 +741,15 @@ usb_otg_pwren: usb-otg-pwren { }; }; + + wifi { + usb_wifi_pwr: usb-wifi-pwr { + rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + wifi_en_h: wifi-en-h { + rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; }; &sdmmc { From e6066edc9413191479b05596ba06c40908f44e22 Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Mon, 30 Jun 2025 12:19:27 +0200 Subject: [PATCH 08/29] arm64: dts: rockchip: add HDMI audio on ROCK 4D Much like the Sige5, the ROCK 4D also has an HDMI port, so is capable of providing HDMI audio output as well. Enable the SoC's hdmi_sound card, and also enable the SoC audio controller (sai6) that feeds into it. Signed-off-by: Nicolas Frattaroli Tested-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20250630-rock4d-audio-v1-4-0b3c8e8fda9c@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts index c2683c2a2f04..9bc33422ced5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts @@ -304,6 +304,10 @@ hdmi_out_con: endpoint { }; }; +&hdmi_sound { + status = "okay"; +}; + &hdptxphy { status = "okay"; }; @@ -752,6 +756,10 @@ wifi_en_h: wifi-en-h { }; }; +&sai6 { + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; From 304be20e65ca08fc2e9cb58eb939a0054d8a8b81 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 27 Jun 2025 12:53:55 +0200 Subject: [PATCH 09/29] arm64: dts: rockchip: add header for RK8XX PMIC constants To make it easier to read the device tree, let's add constants for the rockchip,reset-mode property values that are currently only applicable to RK806 PMIC. Signed-off-by: Quentin Schulz [dt-maintainers did not consider this part of the binding, so we're keeping the header in the devicetree directory] Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-3-ce05d041b45f@cherry.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk8xx.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk8xx.h diff --git a/arch/arm64/boot/dts/rockchip/rk8xx.h b/arch/arm64/boot/dts/rockchip/rk8xx.h new file mode 100644 index 000000000000..a6fbef71c064 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk8xx.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ +/* + * Device Tree defines for Rockchip RK8xx PMICs + * + * Copyright 2025 Cherry Embedded Solutions GmbH + * + * Author: Quentin Schulz + */ + +#ifndef _DT_MFD_ROCKCHIP_RK8XX_H +#define _DT_MFD_ROCKCHIP_RK8XX_H + +/* For use with rockchip,reset-mode property */ +#define RK806_RESTART 0 +#define RK806_RESET 1 +#define RK806_RESET_NOTIFY 2 + +#endif From ee907113430aa02a8202c91bb574c385ecc28aa2 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 27 Jun 2025 12:53:56 +0200 Subject: [PATCH 10/29] arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Jaguar The bootloader for RK3588 Jaguar currently forces the PMIC reset behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X which is incorrect for our devices. It is required to restart the PMU as otherwise the companion microcontroller cannot detect the PMIC (and by extension the full product and main SoC) being rebooted which is an issue as that is used to reset a few things like the PWM beeper and watchdogs. Let's add the new rockchip,reset-mode property to make sure the PMIC reset behavior is the expected one. Signed-off-by: Quentin Schulz Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-4-ce05d041b45f@cherry.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index ebe77cdd24e8..176925d0a1a8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -10,6 +10,7 @@ #include #include #include +#include "rk8xx.h" #include "rk3588.dtsi" / { @@ -693,6 +694,7 @@ pmic@0 { vcc13-supply = <&vcc_1v1_nldo_s3>; vcc14-supply = <&vcc_1v1_nldo_s3>; vcca-supply = <&vcc5v0_sys>; + rockchip,reset-mode = ; rk806_dvs1_null: dvs1-null-pins { pins = "gpio_pwrctrl1"; From e82f642b9821384045915dc30e73df7de8424827 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 27 Jun 2025 12:53:57 +0200 Subject: [PATCH 11/29] arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Tiger The bootloader for RK3588 Tiger currently forces the PMIC reset behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X which is incorrect for our devices. It is required to restart the PMU as otherwise the companion microcontroller cannot detect the PMIC (and by extension the full product and main SoC) being rebooted which is an issue as that is used to reset a few things like the PWM beeper and watchdogs. Let's add the new rockchip,reset-mode property to make sure the PMIC reset behavior is the expected one. Signed-off-by: Quentin Schulz Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-5-ce05d041b45f@cherry.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index c4933a08dd1e..b44e89e1bb15 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include "rk8xx.h" #include "rk3588.dtsi" / { @@ -440,6 +441,7 @@ pmic@0 { vcc13-supply = <&vcc_1v1_nldo_s3>; vcc14-supply = <&vcc_1v1_nldo_s3>; vcca-supply = <&vcc5v0_sys>; + rockchip,reset-mode = ; rk806_dvs1_null: dvs1-null-pins { pins = "gpio_pwrctrl1"; From 863993ff9c6c0e6ecaf942e0d625e5df134e464f Mon Sep 17 00:00:00 2001 From: John Clark Date: Sat, 28 Jun 2025 10:32:28 -0400 Subject: [PATCH 12/29] dt-bindings: arm: rockchip: add FriendlyElec NanoPi M5 board Add device tree documentation for rk3576-nanopi-m5 Signed-off-by: John Clark Acked-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250628143229.74460-2-inindev@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 58b9312c6c73..28db6bd6aa5b 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -300,6 +300,12 @@ properties: - friendlyarm,nanopi-r4s-enterprise - const: rockchip,rk3399 + - description: FriendlyElec NanoPi M5 series boards + items: + - enum: + - friendlyarm,nanopi-m5 + - const: rockchip,rk3576 + - description: FriendlyElec NanoPi R5 series boards items: - enum: From 96cbdfdd3ac20700b9b1c251fb15c944f33a424a Mon Sep 17 00:00:00 2001 From: John Clark Date: Sat, 28 Jun 2025 10:32:29 -0400 Subject: [PATCH 13/29] arm64: dts: rockchip: Add FriendlyElec NanoPi M5 support Add device tree for FriendlyElec NanoPi M5 with Rockchip RK3576 SoC (4x Cortex-A72, 4x Cortex-A53, Mali-G52 MC3 GPU, 6 TOPS NPU). Enables basic booting and connectivity. Supported features: - RK3576 SoC - 4GB LPDDR4X or 8GB/16GB LPDDR5 - 16MB SPI Nor Flash - 2x 1Gbps Ethernet - 2x USB 3.2 Gen 1 Type-A ports - M.2 M-Key PCIe 2.1 x1 NVMe support - M.2 E-Key SDIO connector - microSD UHS-I - HDMI 1.4/2.0 (up to 4096x2304@60Hz) - 30-pin GPIO (2x SPI, 4x UART, 3x I2C, 5x PWM, 20x GPIO) - Debug UART - RTC with HYM8563TS - Power via USB-C (PD, 6V~20V) Signed-off-by: John Clark Link: https://lore.kernel.org/r/20250628143229.74460-3-inindev@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3576-nanopi-m5.dts | 941 ++++++++++++++++++ 2 files changed, 942 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index e43565c53c56..099520962ffb 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -148,6 +148,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5-v1.2-wifibt.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-luckfox-omni3576.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-m5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-rock-4d.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3582-radxa-e52c.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts new file mode 100644 index 000000000000..cce34c541f7c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts @@ -0,0 +1,941 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 FriendlyElec Computer Tech. Co., Ltd. + * Copyright (c) 2025 John Clark + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include "rk3576.dtsi" + +/ { + model = "FriendlyElec NanoPi M5"; + compatible = "friendlyarm,nanopi-m5", "rockchip,rk3576"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + hdmi-pwr-supply = <&vcc5v_hdmi_tx>; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + keys { + compatible = "gpio-keys"; + + usr_button: key-1 { + debounce-interval = <50>; + gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_LOW>; + label = "user"; + linux,code = ; + pinctrl-names = "default"; + pinctrl-0 = <&usr_button_l>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_sys: led-0 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + label = "sys"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_sys_h>; + }; + + led1: led-1 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + label = "led1"; + linux,default-trigger = "netdev"; + pinctrl-names = "default"; + pinctrl-0 = <&led1_h>; + }; + + led2: led-2 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + label = "led2"; + linux,default-trigger = "netdev"; + pinctrl-names = "default"; + pinctrl-0 = <&led2_h>; + }; + }; + + usb3_port2_5v: regulator-usb3-port2-5v { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_host_pwren_h>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "usb3_port2_5v"; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc12v_dcin"; + }; + + vcc3v3_m2_keym: regulator-vcc3v3-m2-keym { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pwren_h>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_m2_keym"; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc3v3_sd_s0: regulator-vcc3v3-sd-s0 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwren_h>; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sd_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc5v0_sys_s5: regulator-vcc5v0-sys-s5 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys_s5"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg0_pwren_h>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_usb_otg0"; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc5v_hdmi_tx: regulator-vcc5v-hdmi-tx { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v_hdmi_tx"; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vcc_1v1_nldo_s3"; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vcc_2v0_pldo_s3"; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det_l>; + + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "realtek,rt5616-codec"; + + simple-audio-card,routing = + "Headphones", "HPOL", + "Headphones", "HPOR", + "IN1P", "Microphone Jack"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Microphone", "Microphone Jack"; + + simple-audio-card,codec { + sound-dai = <&rt5616>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&fspi1m1_pins { + /* gpio1_d5, gpio1_c4-c7 (clk, d0-d4) are for spi nor flash */ + /* gpio1_d0-d4 muxed to sai2 audio functions */ + rockchip,pins = + <1 RK_PD5 3 &pcfg_pull_none>, + <1 RK_PC4 3 &pcfg_pull_none>, + <1 RK_PC5 3 &pcfg_pull_none>, + <1 RK_PC6 3 &pcfg_pull_none>, + <1 RK_PC7 3 &pcfg_pull_none>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3_s3>; + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim>, + <ð0m0_tx_bus2>, + <ð0m0_rx_bus2>, + <ð0m0_rgmii_clk>, + <ð0m0_rgmii_bus>; + status = "okay"; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3_s3>; + pinctrl-names = "default"; + pinctrl-0 = <ð1m0_miim>, + <ð1m0_tx_bus2>, + <ð1m0_rx_bus2>, + <ð1m0_rgmii_clk>, + <ð1m0_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys_s5>; + vcc2-supply = <&vcc5v0_sys_s5>; + vcc3-supply = <&vcc5v0_sys_s5>; + vcc4-supply = <&vcc5v0_sys_s5>; + vcc5-supply = <&vcc5v0_sys_s5>; + vcc6-supply = <&vcc5v0_sys_s5>; + vcc7-supply = <&vcc5v0_sys_s5>; + vcc8-supply = <&vcc5v0_sys_s5>; + vcc9-supply = <&vcc5v0_sys_s5>; + vcc10-supply = <&vcc5v0_sys_s5>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys_s5>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys_s5>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_big_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd_gpu_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda0v75_hdmi_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2c5 { + clock-frequency = <200000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + status = "okay"; + + rt5616: audio-codec@1b { + compatible = "realtek,rt5616"; + reg = <0x1b>; + assigned-clocks = <&cru CLK_SAI2_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru CLK_SAI2_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC0_OUT>; + interrupt-parent = <&gpio2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_int>, <&gmac0_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC1_OUT>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_int>, <&gmac1_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_perstn>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_m2_keym>; + status = "okay"; +}; + +&pinctrl { + gmac { + gmac0_int: gmac0-int { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + gmac0_rst: gmac0-rst { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + gmac1_int: gmac1-int { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + gmac1_rst: gmac1-rst { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + usr_button_l: usr-button-l { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + led_sys_h: led-sys-h { + rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led1_h: led1-h { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led2_h: led2-h { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie0_pwren_h: pcie0-pwren-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie0_perstn: pcie0-perstn { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc0_pwren_h: sdmmc0-pwren-h { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sound { + hp_det_l: hp-det-l { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb3_host_pwren_h: usb3-host-pwren-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + usb_otg0_pwren_h: usb-otg0-pwren-h { + rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sai2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8_s0>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_det>, <&sdmmc0_bus4>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc3v3_sd_s0>; + status = "okay"; +}; + +&sfc1 { + pinctrl-names = "default"; + pinctrl-0 = <&fspi1m1_csn0>, <&fspi1m1_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + vcc-supply = <&vcc_1v8_s3>; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vcc5v0_usb_otg0>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&usb3_port2_5v>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usbdp_phy { + status = "okay"; +}; + +&usb_drd0_dwc3 { + dr_mode = "otg"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&usb_drd1_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&wdt { + status = "okay"; +}; From f2792bf1c7a54ef23fb3a84286b66f427bfc4853 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 21 Jun 2025 11:38:57 +0000 Subject: [PATCH 14/29] arm64: dts: rockchip: Fix pinctrl node names for RK3528 Following warnings can be observed with CHECK_DTBS=y for the RK3528: rk3528-pinctrl.dtsi:101.36-105.5: Warning (node_name_chars_strict): /pinctrl/fephy/fephym0-led_dpx: Character '_' not recommended in node name rk3528-pinctrl.dtsi:108.38-112.5: Warning (node_name_chars_strict): /pinctrl/fephy/fephym0-led_link: Character '_' not recommended in node name rk3528-pinctrl.dtsi:115.36-119.5: Warning (node_name_chars_strict): /pinctrl/fephy/fephym0-led_spd: Character '_' not recommended in node name rk3528-pinctrl.dtsi:122.36-126.5: Warning (node_name_chars_strict): /pinctrl/fephy/fephym1-led_dpx: Character '_' not recommended in node name rk3528-pinctrl.dtsi:129.38-133.5: Warning (node_name_chars_strict): /pinctrl/fephy/fephym1-led_link: Character '_' not recommended in node name rk3528-pinctrl.dtsi:136.36-140.5: Warning (node_name_chars_strict): /pinctrl/fephy/fephym1-led_spd: Character '_' not recommended in node name rk3528-pinctrl.dtsi:782.32-790.5: Warning (node_name_chars_strict): /pinctrl/rgmii/rgmii-rx_bus2: Character '_' not recommended in node name rk3528-pinctrl.dtsi:793.32-801.5: Warning (node_name_chars_strict): /pinctrl/rgmii/rgmii-tx_bus2: Character '_' not recommended in node name rk3528-pinctrl.dtsi:804.36-810.5: Warning (node_name_chars_strict): /pinctrl/rgmii/rgmii-rgmii_clk: Character '_' not recommended in node name rk3528-pinctrl.dtsi:813.36-823.5: Warning (node_name_chars_strict): /pinctrl/rgmii/rgmii-rgmii_bus: Character '_' not recommended in node name Rename the affected nodes to fix these warnings. Fixes: a31fad19ae39 ("arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528") Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20250621113859.2146400-1-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3528-pinctrl.dtsi | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi index ea051362fb26..59b75c91bbb7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi @@ -98,42 +98,42 @@ eth_pins: eth-pins { fephy { /omit-if-no-ref/ - fephym0_led_dpx: fephym0-led_dpx { + fephym0_led_dpx: fephym0-led-dpx { rockchip,pins = /* fephy_led_dpx_m0 */ <4 RK_PB5 2 &pcfg_pull_none>; }; /omit-if-no-ref/ - fephym0_led_link: fephym0-led_link { + fephym0_led_link: fephym0-led-link { rockchip,pins = /* fephy_led_link_m0 */ <4 RK_PC0 2 &pcfg_pull_none>; }; /omit-if-no-ref/ - fephym0_led_spd: fephym0-led_spd { + fephym0_led_spd: fephym0-led-spd { rockchip,pins = /* fephy_led_spd_m0 */ <4 RK_PB7 2 &pcfg_pull_none>; }; /omit-if-no-ref/ - fephym1_led_dpx: fephym1-led_dpx { + fephym1_led_dpx: fephym1-led-dpx { rockchip,pins = /* fephy_led_dpx_m1 */ <2 RK_PA4 5 &pcfg_pull_none>; }; /omit-if-no-ref/ - fephym1_led_link: fephym1-led_link { + fephym1_led_link: fephym1-led-link { rockchip,pins = /* fephy_led_link_m1 */ <2 RK_PA6 5 &pcfg_pull_none>; }; /omit-if-no-ref/ - fephym1_led_spd: fephym1-led_spd { + fephym1_led_spd: fephym1-led-spd { rockchip,pins = /* fephy_led_spd_m1 */ <2 RK_PA5 5 &pcfg_pull_none>; @@ -779,7 +779,7 @@ rgmii_miim: rgmii-miim { }; /omit-if-no-ref/ - rgmii_rx_bus2: rgmii-rx_bus2 { + rgmii_rx_bus2: rgmii-rx-bus2 { rockchip,pins = /* rgmii_rxd0 */ <3 RK_PA3 2 &pcfg_pull_none>, @@ -790,7 +790,7 @@ rgmii_rx_bus2: rgmii-rx_bus2 { }; /omit-if-no-ref/ - rgmii_tx_bus2: rgmii-tx_bus2 { + rgmii_tx_bus2: rgmii-tx-bus2 { rockchip,pins = /* rgmii_txd0 */ <3 RK_PA1 2 &pcfg_pull_none_drv_level_2>, @@ -801,7 +801,7 @@ rgmii_tx_bus2: rgmii-tx_bus2 { }; /omit-if-no-ref/ - rgmii_rgmii_clk: rgmii-rgmii_clk { + rgmii_rgmii_clk: rgmii-rgmii-clk { rockchip,pins = /* rgmii_rxclk */ <3 RK_PA5 2 &pcfg_pull_none>, @@ -810,7 +810,7 @@ rgmii_rgmii_clk: rgmii-rgmii_clk { }; /omit-if-no-ref/ - rgmii_rgmii_bus: rgmii-rgmii_bus { + rgmii_rgmii_bus: rgmii-rgmii-bus { rockchip,pins = /* rgmii_rxd2 */ <3 RK_PA7 2 &pcfg_pull_none>, From 9336eb829a18bba910620cb2e3fc55fcdd4aeecc Mon Sep 17 00:00:00 2001 From: Olivier Benjamin Date: Fri, 20 Jun 2025 17:21:34 +0200 Subject: [PATCH 15/29] arm64: dts: rockchip: describe I2c Bus 1 and IMX258 world camera on PinePhone Pro Add the description of the rear/world camera (IMX258) on the PinePhone Pro to the device dts file. It receives commands on the I2C Bus 1 at address 0x1a and transmits data over CSI-MIPI. The I2C address for IMX258 can be found in the IMX258-0AQH5 Software Reference Manual, page 24, section 2.3.1: 0b0011010 = 0x1a. Section 3 indicates the module has 4 pairs of data lines. While 4-lane mode is nominal, 2-lane mode should also be supported. The pin muxing info was extracted from the PinePhone Pro schematic v1.0 as well as the RK3399 datasheet revision 1.8. Table 2-3 in section 2.8 of the RK3399 datasheet contains the mapping of IO functions for the SoC pins. Page 52 shows GPIO1_A0, page 54 shows GPIO2_D4. For I2C power, the PinePhone Pro schematic page 11 quadrants A4 and A5: RK3399_J.AA8 and RK3399_J.Y8 get power from vcaa1v8_codec, so turn it on The IMX258 also uses the following regulators, expected by its driver: - vana (2.8V analog), called AVDD2V8_DVP on P.18 q.C1 and derived from VCC1V8_S3 on P.13 q.B2 - vdig (1.2V digital core), called DVDD_DVP on P.18 q.C1 and shown on P.18 q.D3 to be equivalent to VCC1V2_DVP derived from VCC3V3_SYS on P.13 q.B3. Note that this regulator's voltage is inconsistently labeled either 1.2V or 1.5V RK3399_J.AG1 is GPIO4_A1/I2C1_SDA, RK3399_J.Y6 is GPIO4_A2/I2C1_SCL This is the default pinctrl "i2c1_xfer" for i2c1 from rk3399-base. For the reset (RESET) signal: page 11 quadrant D2 | p.18 q.C3-4 | p.18 q.C2 RK3399_E.R25 -> GPIO1_A0 -> Camera_RST -> MIPI_RST0 -> IMX258.12 For the powerdown (PWDN) signal: page 11 quadrants B4-5 | p.18 q.C2 RK3399_G.AF8 -> GPIO2_D4 -> DVP_PDN1_H -> IMX258.14 Helped-by: Dragan Simic Co-developed-by: Ondrej Jirman Signed-off-by: Ondrej Jirman Signed-off-by: Olivier Benjamin Link: https://lore.kernel.org/r/20250620-camera-v4-3-0201a8ed5fae@bootlin.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-pinephone-pro.dts | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 909ed14035f7..8418be9e2d62 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -104,6 +104,16 @@ vcc_sys: regulator-vcc-sys { regulator-boot-on; }; + avdd2v8_dvp: regulator-avdd2v8-dvp { + compatible = "regulator-fixed"; + regulator-name = "avdd2v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc3v3_sys>; + }; + vcc3v3_sys: regulator-vcc3v3-sys { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; @@ -136,6 +146,16 @@ vcc1v8_codec: regulator-vcc1v8-codec { vin-supply = <&vcc3v3_sys>; }; + vcc1v2_dvp: regulator-vcc1v2-dvp { + compatible = "regulator-fixed"; + regulator-name = "vcc1v2_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcca1v8_s3>; + }; + wifi_pwrseq: sdio-wifi-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rk818 1>; @@ -312,6 +332,8 @@ vcc3v0_touch: LDO_REG2 { vcca1v8_codec: LDO_REG3 { regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; @@ -420,6 +442,46 @@ regulator-state-mem { }; }; +&i2c1 { + assigned-clocks = <&cru SCLK_CIF_OUT>; + assigned-clock-rates = <24000000>; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer &cif_clkouta>; + status = "okay"; + + wcam: camera@1a { + compatible = "sony,imx258"; + reg = <0x1a>; + clocks = <&cru SCLK_CIF_OUT>; /* MIPI_MCLK0, derived from CIF_CLKO */ + lens-focus = <&wcam_lens>; + orientation = <1>; /* V4L2_CAMERA_ORIENTATION_BACK */ + pinctrl-names = "default"; + pinctrl-0 = <&camera_rst_l>; + reset-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_LOW>; + rotation = <270>; + /* Note: both cameras also depend on vcca1v8_codec to power the I2C bus. */ + vif-supply = <&vcc1v8_dvp>; + vana-supply = <&avdd2v8_dvp>; + vdig-supply = <&vcc1v2_dvp>; /* DVDD_DVP is the same as VCC1V2_DVP */ + + port { + wcam_out: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <636000000>; + remote-endpoint = <&mipi_in_wcam>; + }; + }; + }; + + wcam_lens: camera-lens@c { + compatible = "dongwoon,dw9714"; + reg = <0x0c>; + /* Same I2c bus as both cameras, depends on vcca1v8_codec for power. */ + vcc-supply = <&vcc1v8_dvp>; + }; +}; + &i2c3 { i2c-scl-rising-time-ns = <450>; i2c-scl-falling-time-ns = <15>; @@ -462,6 +524,28 @@ &io_domains { status = "okay"; }; +&isp1 { + status = "okay"; + + ports { + port@0 { + mipi_in_wcam: endpoint@0 { + reg = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&wcam_out>; + }; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + &mipi_dsi { clock-master; status = "okay"; @@ -490,6 +574,10 @@ mipi_out_panel: endpoint { }; }; +&mipi_dsi1 { + status = "okay"; +}; + &pmu_io_domains { pmu1830-supply = <&vcc_1v8>; status = "okay"; @@ -508,6 +596,12 @@ lcd1_rst_pin: lcd1-rst-pin { }; }; + camera { + camera_rst_l: camera-rst-l { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { red_led_pin: red-led-pin { rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; From b45f9f910aa28fc6151ac5d1ff107522b4a6b1af Mon Sep 17 00:00:00 2001 From: Olivier Benjamin Date: Fri, 20 Jun 2025 17:21:35 +0200 Subject: [PATCH 16/29] arm64: dts: rockchip: describe the OV8858 user camera on PinePhone Pro Add the description of the front/user camera (OV8858) on the PinePhone Pro to the device dts file. It receives commands over SCCB, an I2C-compatible protocol, at I2C address 0x36 and transmits data over CSI-MIPI. I confirmed this address experimentally. The pin control mapping was again extracted from the PinePhone Pro schematic v1.0 as well as the RK3399 datasheet revision 1.8. Table 2-3 in section 2.8 of the RK3399 datasheet contains the mapping of IO functions for the SoC pins. Page 52 shows GPIO1_A4, page 54 shows GPIO2_B4. For the reset (RESET) signal: page 11 quadrant D2 | p.18 q.B3-4 | p.18 q.C2 RK3399_E.R28 -> GPIO1_A4 -> Camera2_RST -> MIPI_RST1 -> OV8858.12 For the powerdown (PWDN) signal: page 9 quadrants D4-5 | p.18 q.B2 RK3399_L.F31 -> GPIO2_B4 -> DVP_PDN0_H -> OV8858.14 Helped-by: Dragan Simic Co-developed-by: Ondrej Jirman Signed-off-by: Ondrej Jirman Signed-off-by: Olivier Benjamin Link: https://lore.kernel.org/r/20250620-camera-v4-4-0201a8ed5fae@bootlin.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-pinephone-pro.dts | 47 ++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 8418be9e2d62..780b4224fd56 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -480,6 +480,27 @@ wcam_lens: camera-lens@c { /* Same I2c bus as both cameras, depends on vcca1v8_codec for power. */ vcc-supply = <&vcc1v8_dvp>; }; + + ucam: camera@36 { + compatible = "ovti,ov8858"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; /* MIPI_MCLK1, derived from CIF_CLK0 */ + clock-names = "xvclk"; + dovdd-supply = <&vcc1v8_dvp>; + orientation = <0>; /* V4L2_CAMERA_ORIENTATION_FRONT */ + pinctrl-names = "default"; + pinctrl-0 = <&camera2_rst_l &dvp_pdn0_h>; + powerdown-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + rotation = <90>; + + port { + ucam_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&mipi_in_ucam>; + }; + }; + }; }; &i2c3 { @@ -524,6 +545,24 @@ &io_domains { status = "okay"; }; +&isp0 { + status = "okay"; + + ports { + port@0 { + mipi_in_ucam: endpoint@0 { + reg = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&ucam_out>; + }; + }; + }; +}; + +&isp0_mmu { + status = "okay"; +}; + &isp1 { status = "okay"; @@ -596,10 +635,16 @@ lcd1_rst_pin: lcd1-rst-pin { }; }; - camera { + cameras { camera_rst_l: camera-rst-l { rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; }; + camera2_rst_l: camera2-rst-l { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + dvp_pdn0_h: dvp-pdn0-h { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; leds { From a2df3aead3e023857330a803c664ee97a7bd9b97 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Sun, 13 Jul 2025 18:16:36 +0200 Subject: [PATCH 17/29] arm64: dts: rockchip: Add rtc0 alias for NanoPi R5S + R5C The RTC_HCTOSYS_DEVICE module defaults to rtc0 and should (highly) preferable be assigned to a battery backed RTC module as it is used to (re)initialize the system clock. The R5S and R5C have a connector for a RTC battery which is used by HYM8563 RTC. Both devices also have another RTC from the rk809 PMIC. To make sure the HYM8563 is always assigned rtc0, add an alias for it. Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250713161723.270963-1-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi index a28b4af10d13..f4d042bdd328 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi @@ -18,6 +18,7 @@ / { aliases { mmc0 = &sdmmc0; mmc1 = &sdhci; + rtc0 = &hym8563; }; chosen: chosen { From 954f07012794a3aa7ae89e56f070eaa1643af50b Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Fri, 11 Jul 2025 16:20:37 +0200 Subject: [PATCH 18/29] arm64: dts: rockchip: Add reset button to NanoPi R5S The NanoPi R5S LTS version has a reset button, which is connected via GPIO. Note that the non-LTS version does not have the reset button and therefore on page 19 of the schematic version 2204 it is marked 'NC', but it is connected on the LTS version. Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250711142138.197445-1-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts index 3b31f0dd8f3b..c12bd01e2805 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts @@ -17,6 +17,19 @@ aliases { ethernet0 = &gmac0; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio4_a0_k1_pin>; + pinctrl-names = "default"; + + button-reset { + debounce-interval = <50>; + gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + label = "RESET"; + linux,code = ; + }; + }; + gpio-leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -127,6 +140,12 @@ eth_phy0_reset_pin: eth-phy0-reset-pin { }; }; + gpio-keys { + gpio4_a0_k1_pin: gpio4-a0-k1-pin { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + gpio-leds { lan1_led_pin: lan1-led-pin { rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; From ae019f0bdfbef3e0671e7b954321e92fc24c7e54 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 9 Jul 2025 21:08:28 +0000 Subject: [PATCH 19/29] arm64: dts: rockchip: Fix UART DMA support for RK3528 Trying to use UART2 DMA for Bluetooth on ArmSoM Sige1 result in tx timeout when using dma-names = "tx", "rx" as required by the dt-binding: Bluetooth: hci0: command 0x0c03 tx timeout Bluetooth: hci0: BCM: Reset failed (-110) Change the dmas order to fix UART DMA support on RK3528. With this fixed Bluetooth can be loaded using DMA on ArmSoM Sige1: Bluetooth: hci0: BCM: chip id 159 Bluetooth: hci0: BCM: features 0x0f Bluetooth: hci0: BCM4362A2 Bluetooth: hci0: BCM4362A2 (000.017.017) build 0000 Bluetooth: hci0: BCM4362A2 'brcm/BCM4362A2.hcd' Patch Bluetooth: hci0: BCM: features 0x0f Bluetooth: hci0: BCM43752A2 UART 37.4MHz Ampak AP6398 sLNA iLNA CL1 [Version: 1091.1173] Bluetooth: hci0: BCM4362A2 (000.017.017) build 1173 Fixes: ab6fcb58aedf ("arm64: dts: rockchip: Add UART DMA support for RK3528") Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20250709210831.3170458-1-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index b215126efcc2..001a555c83b7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -595,7 +595,7 @@ uart0: serial@ff9f0000 { clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; interrupts = ; - dmas = <&dmac 8>, <&dmac 9>; + dmas = <&dmac 9>, <&dmac 8>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -607,7 +607,7 @@ uart1: serial@ff9f8000 { clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; interrupts = ; - dmas = <&dmac 10>, <&dmac 11>; + dmas = <&dmac 11>, <&dmac 10>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -619,7 +619,7 @@ uart2: serial@ffa00000 { clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; interrupts = ; - dmas = <&dmac 12>, <&dmac 13>; + dmas = <&dmac 13>, <&dmac 12>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -631,7 +631,7 @@ uart3: serial@ffa08000 { clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; interrupts = ; - dmas = <&dmac 14>, <&dmac 15>; + dmas = <&dmac 15>, <&dmac 14>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -643,7 +643,7 @@ uart4: serial@ffa10000 { clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; clock-names = "baudclk", "apb_pclk"; interrupts = ; - dmas = <&dmac 16>, <&dmac 17>; + dmas = <&dmac 17>, <&dmac 16>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -655,7 +655,7 @@ uart5: serial@ffa18000 { clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; clock-names = "baudclk", "apb_pclk"; interrupts = ; - dmas = <&dmac 18>, <&dmac 19>; + dmas = <&dmac 19>, <&dmac 18>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -667,7 +667,7 @@ uart6: serial@ffa20000 { clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; clock-names = "baudclk", "apb_pclk"; interrupts = ; - dmas = <&dmac 20>, <&dmac 21>; + dmas = <&dmac 21>, <&dmac 20>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -679,7 +679,7 @@ uart7: serial@ffa28000 { clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; clock-names = "baudclk", "apb_pclk"; interrupts = ; - dmas = <&dmac 22>, <&dmac 23>; + dmas = <&dmac 23>, <&dmac 22>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; From 98921ad2494a85aa7edde33a3a478b9ae3d621ef Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Wed, 9 Jul 2025 15:15:14 +0200 Subject: [PATCH 20/29] arm64: dts: rockchip: Move dsi address+size-cells from SoC to px30 boards The #address-cells and #size-cells properties are not useful on the DSI controller node; they are only useful/required on ports and panel(s). So remove them from the controller node and add them where actually needed on the various px30 based boards, which includes rk3326. This fixes the following DTB validation warnings: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" property Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250709132323.128757-2-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts | 2 ++ arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts | 2 ++ arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts | 2 ++ arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts | 2 ++ arch/arm64/boot/dts/rockchip/px30-evb.dts | 2 ++ arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts | 2 ++ arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts | 2 ++ arch/arm64/boot/dts/rockchip/px30.dtsi | 2 -- arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dtsi | 2 ++ arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts | 2 ++ arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi | 2 ++ 11 files changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts index 1d26164be7b8..a31c61c8f148 100644 --- a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts +++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts @@ -12,6 +12,8 @@ / { }; &dsi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; panel@0 { diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts index 82c6acdb4fae..a3c6edfdb37c 100644 --- a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts +++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts @@ -12,6 +12,8 @@ / { }; &dsi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; panel@0 { diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts index 94449132df38..9b5eff392dfa 100644 --- a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts +++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts @@ -12,6 +12,8 @@ / { }; &dsi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; panel@0 { diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts index d7b639e7ccab..36b7cae49e31 100644 --- a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts +++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts @@ -16,6 +16,8 @@ aliases { }; &dsi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; panel@0 { diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts index bfd724b73c9a..85d1642eb9be 100644 --- a/arch/arm64/boot/dts/rockchip/px30-evb.dts +++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts @@ -124,6 +124,8 @@ &display_subsystem { }; &dsi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; ports { diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts index b71929bcb33e..932721ffd470 100644 --- a/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts +++ b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts @@ -12,6 +12,8 @@ / { }; &dsi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; panel@0 { diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts index a9bd5936c701..70adf091371c 100644 --- a/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts +++ b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts @@ -12,6 +12,8 @@ / { }; &dsi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; panel@0 { diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 0cad83c5d5fe..5034ad8019a8 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1137,8 +1137,6 @@ dsi: dsi@ff450000 { resets = <&cru SRST_MIPIDSI_HOST_P>; reset-names = "apb"; rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; ports { diff --git a/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dtsi b/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dtsi index 150fadcb0b3c..54395a40b087 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dtsi @@ -118,6 +118,8 @@ &display_subsystem { }; &dsi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; ports { diff --git a/arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts b/arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts index 10e6ab724ac4..4d306085646c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts +++ b/arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts @@ -322,6 +322,8 @@ &display_subsystem { }; &dsi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; internal_display: panel@0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi index 446a1a6c12e7..bf4554eff47d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi @@ -220,6 +220,8 @@ &display_subsystem { }; &dsi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; ports { From d9c9115c6127636efbdc0fad8184bed1cd42fe3c Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Wed, 9 Jul 2025 15:15:15 +0200 Subject: [PATCH 21/29] arm64: dts: rockchip: Move dsi address+size-cells from SoC to rk3399 boards The #address-cells and #size-cells properties are not useful on the DSI controller node; they are only useful/required on ports and panel(s). So remove them from the controller node and add them where actually needed on the various rk3399 based boards. This fixes the following DTB validation warnings: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" property Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250709132323.128757-3-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 4 ---- arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 4 +++- arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 2 ++ arch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso | 3 +-- 4 files changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi index 9d5f5b083e3c..4dcceb9136b7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi @@ -2071,8 +2071,6 @@ mipi_dsi: dsi@ff960000 { resets = <&cru SRST_P_MIPI_DSI0>; reset-names = "apb"; rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; ports { @@ -2112,8 +2110,6 @@ mipi_dsi1: dsi@ff968000 { resets = <&cru SRST_P_MIPI_DSI1>; reset-names = "apb"; rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; #phy-cells = <0>; status = "disabled"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index 5e068377a0a2..6aaaf0f7f73f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -627,8 +627,10 @@ &mipi_dphy_rx0 { }; &mipi_dsi { - status = "okay"; clock-master; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; ports { mipi_out: port@1 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 780b4224fd56..585ef0fd88ef 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -587,6 +587,8 @@ &isp1_mmu { &mipi_dsi { clock-master; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; panel@0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso index b1f4ab22b99c..a26c8e05c13b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso @@ -47,10 +47,9 @@ touch: touchscreen@5d { }; &mipi_dsi { + clock-master; #address-cells = <1>; #size-cells = <0>; - - clock-master; status = "okay"; ports { From 776d8e75d4a3a422a680648e30c5bfe607a99805 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Wed, 9 Jul 2025 15:15:17 +0200 Subject: [PATCH 22/29] arm64: dts: rockchip: Simplify VOP port definition on rk3328 When there's only 1 endpoint, there is no need for a unit-address and removing that allows removing of related properties as well. This fixes the following DTB validation warnings: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250709132323.128757-5-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 7d992c3c01ce..6438c969f9d7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -731,11 +731,7 @@ vop: vop@ff370000 { status = "disabled"; vop_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop_out_hdmi: endpoint@0 { - reg = <0>; + vop_out_hdmi: endpoint { remote-endpoint = <&hdmi_in_vop>; }; }; From 25937eb02f0a5a7e30fe97333ecc94ec5582ecb3 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Wed, 9 Jul 2025 15:15:18 +0200 Subject: [PATCH 23/29] arm64: dts: rockchip: Simplify edp endpoints on several rk3399 boards The only thing actually added here is a single endpoint on edp_out, which is already defined in rk3399-base.dtsi, so it's simpler to just reference that phandle, which allows the removal of several properties. This fixes the following DTB validation warnings: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250709132323.128757-6-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-gru-chromebook.dtsi | 15 ++++----------- .../boot/dts/rockchip/rk3399-pinebook-pro.dts | 15 ++++----------- .../dts/rockchip/rk3399-sapphire-excavator.dts | 18 +++++------------- 3 files changed, 13 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index a9ea4b0daa04..9d07353df52c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -250,18 +250,11 @@ &edp { */ assigned-clocks = <&cru PCLK_EDP>; assigned-clock-rates = <24000000>; +}; - ports { - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - edp_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; +&edp_out { + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts index 5473070823cb..5a8551d9ffe4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts @@ -404,18 +404,11 @@ &edp { pinctrl-names = "default"; pinctrl-0 = <&edp_hpd>; status = "okay"; +}; - ports { - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - edp_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; +&edp_out { + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts index fdaa8472b7a7..a4ceafe6dd7a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts @@ -142,21 +142,13 @@ sdio_pwrseq: sdio-pwrseq { &edp { status = "okay"; - - ports { - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - edp_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; }; +&edp_out { + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; +}; &i2c1 { i2c-scl-rising-time-ns = <300>; i2c-scl-falling-time-ns = <15>; From dfb549bbca62fe4b2c06bf203a3a9c1f86fcfae2 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Wed, 9 Jul 2025 15:15:19 +0200 Subject: [PATCH 24/29] arm64: dts: rockchip: Simplify mipi_out endpoint on rk3399 RP64 dtso The only thing actually added here is a single endpoint on mipi_out, which is already defined in rk3399-base.dtsi, so it's simpler to just reference that phandle, which allows the removal of several properties. Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250709132323.128757-7-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-rockpro64-screen.dtso | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso index a26c8e05c13b..dabe535f2111 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso @@ -52,19 +52,6 @@ &mipi_dsi { #size-cells = <0>; status = "okay"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - mipi_out: port@1 { - reg = <1>; - - mipi_out_panel: endpoint { - remote-endpoint = <&mipi_in_panel>; - }; - }; - }; - mipi_panel: panel@0 { compatible = "feiyang,fy07024di26a30d"; reg = <0>; @@ -80,6 +67,12 @@ mipi_in_panel: endpoint { }; }; +&mipi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; + &pwm0 { status = "okay"; }; From 4ac334d40e7022f091c65480cb7a01bc89135989 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Wed, 9 Jul 2025 15:15:20 +0200 Subject: [PATCH 25/29] arm64: dts: rockchip: Move mipi_out node on rk3399 haikou demo dtso According to the DTS coding style [1] referenced nodes should be sorted alpha-numerically so move mipi_out to be after mipi_in_panel. [1] https://www.kernel.org/doc/html/latest/devicetree/bindings/dts-coding-style.html#order-of-nodes Signed-off-by: Diederik de Haas Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20250709132323.128757-8-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-puma-haikou-video-demo.dtso | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso index 0377ec860d35..d28880b8dd44 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso @@ -124,12 +124,6 @@ pca9670: gpio@27 { }; }; -&mipi_out { - mipi_out_panel: endpoint { - remote-endpoint = <&mipi_in_panel>; - }; -}; - &mipi_dsi { #address-cells = <1>; #size-cells = <0>; @@ -151,6 +145,12 @@ mipi_in_panel: endpoint { }; }; +&mipi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; + &pinctrl { pca9670 { pca9670_resetn: pca9670-resetn { From 8c17c938dd94f70fd37db476f8b965dd2775b874 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Wed, 9 Jul 2025 15:15:21 +0200 Subject: [PATCH 26/29] arm64: dts: rockchip: Fix LCD panel port on rk3566-pinetab2 The MIPI DSI connector on the PineTab2 only has 1 port with 1 endpoint, so drop the unit-address properties. While at it, move 'rotation' property to its proper sorting position. This fixes the following DTB validation warnings: node has a unit name, but no reg or ranges property Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250709132323.128757-9-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi index 3473b1eef5cd..d0e38412d56a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi @@ -282,11 +282,11 @@ lcd: panel@0 { reg = <0>; backlight = <&backlight>; enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - rotation = <90>; power-supply = <&vcc_3v3>; + rotation = <90>; - port@0 { - panel_in_dsi: endpoint@0 { + port { + panel_in_dsi: endpoint { remote-endpoint = <&dsi0_out_con>; }; }; From 2fe00f4611637db677be51d7812dc177e4019b6a Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Wed, 9 Jul 2025 15:15:22 +0200 Subject: [PATCH 27/29] arm64: dts: rockchip: Drop unneeded address+size-cells on px30 On nodes with compatible "rockchip,px30-usb2phy-grf", the #address-cells and #size-cells are required and consequently their child nodes should have unit addresses. That is not the case for the px30-pmugrf and px30-grf nodes, so remove them there. This fixes the following DTB validation warnings: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" property Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250709132323.128757-10-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 5034ad8019a8..46f64cd33b9b 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -351,8 +351,6 @@ power-domain@PX30_PD_GPU { pmugrf: syscon@ff010000 { compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff010000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; pmu_io_domains: io-domains { compatible = "rockchip,px30-pmu-io-voltage-domain"; @@ -453,8 +451,6 @@ gic: interrupt-controller@ff131000 { grf: syscon@ff140000 { compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; reg = <0x0 0xff140000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; io_domains: io-domains { compatible = "rockchip,px30-io-voltage-domain"; From b2501f327b8a136dbdd1fe7bad5d113eeda2827a Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Wed, 9 Jul 2025 15:15:23 +0200 Subject: [PATCH 28/29] arm64: dts: rockchip: Drop regulator-compatible property on rk3399 The regulator-compatible property has never existed in the regulator/fcs,fan53555.yaml binding, so drop it. This fixes the following DTB validation warnings: Unevaluated properties are not allowed ('regulator-compatible' was unexpected) Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250709132323.128757-11-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts | 2 -- arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts b/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts index 81c4fcb30f39..352c8efb37e0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts @@ -211,7 +211,6 @@ &i2c0 { vdd_cpu_b: syr827@40 { compatible = "silergy,syr827"; reg = <0x40>; - regulator-compatible = "fan53555-reg"; pinctrl-0 = <&vsel1_pin>; regulator-name = "vdd_cpu_b"; regulator-min-microvolt = <712500>; @@ -229,7 +228,6 @@ regulator-state-mem { vdd_gpu: syr828@41 { compatible = "silergy,syr828"; reg = <0x41>; - regulator-compatible = "fan53555-reg"; pinctrl-0 = <&vsel2_pin>; regulator-name = "vdd_gpu"; regulator-min-microvolt = <712500>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts index 15da5c80d25d..962b8b231c96 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts @@ -421,7 +421,6 @@ vdd_cpu_b: regulator@40 { compatible = "silergy,syr827"; reg = <0x40>; fcs,suspend-voltage-selector = <1>; - regulator-compatible = "fan53555-reg"; pinctrl-0 = <&vsel1_gpio>; vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; regulator-name = "vdd_cpu_b"; @@ -440,7 +439,6 @@ vdd_gpu: regulator@41 { compatible = "silergy,syr828"; reg = <0x41>; fcs,suspend-voltage-selector = <1>; - regulator-compatible = "fan53555-reg"; pinctrl-0 = <&vsel2_gpio>; vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; regulator-name = "vdd_gpu"; From 07e04c071a35abe12957b575cd1453ccafc02eb6 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Wed, 16 Jul 2025 10:33:35 +0200 Subject: [PATCH 29/29] arm64: dts: rockchip: Add maskrom button to NanoPi R5S + R5C Both the R5S and R5C have a MASKROM button connected via saradc. For both the R5S as the R5C it's described on page 9 of their respective schematic, identified as 'Recovery'. Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250716083355.327451-1-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi index f4d042bdd328..e3f44ea4eabe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi @@ -25,6 +25,20 @@ chosen: chosen { stdout-path = "serial2:1500000n8"; }; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "MASKROM"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + hdmi-con { compatible = "hdmi-connector"; type = "a";