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soc: mediatek: mtk-mmsys: Use MMSYS_ROUTE() in default routing table
All of the mtk_mmsys_routes tables for all SoCs were converted to use the MMSYS_ROUTE() macro but the default one used for MT2701, MT2712 and SoCs from that generation was not: convert this one as well. This brings no functional change. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
AngeloGioacchino Del Regno
parent
2fa28edca0
commit
dd63310b94
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@ -158,171 +158,120 @@ struct mtk_mmsys_driver_data {
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* to an independent table.
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*/
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static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {
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{
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DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
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DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
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BLS_TO_DSI_RDMA1_TO_DPI1
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}, {
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DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
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DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
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DSI_SEL_IN_BLS
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}, {
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DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
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BLS_TO_DPI_RDMA1_TO_DSI
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}, {
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DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
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DSI_SEL_IN_RDMA
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}, {
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DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
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DPI_SEL_IN_BLS
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}, {
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DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
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DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
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GAMMA_MOUT_EN_RDMA1
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}, {
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DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
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DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
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OD_MOUT_EN_RDMA0
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}, {
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DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,
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DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
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OD1_MOUT_EN_RDMA1
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
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DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
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OVL0_MOUT_EN_COLOR0
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
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DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
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COLOR0_SEL_IN_OVL0
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
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OVL_MOUT_EN_RDMA
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}, {
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DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
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DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
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OVL1_MOUT_EN_COLOR1
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}, {
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DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
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DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
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COLOR1_SEL_IN_OVL1
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
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RDMA0_SOUT_DPI0
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1,
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DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
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RDMA0_SOUT_DPI1
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1,
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DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
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RDMA0_SOUT_DSI1
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2,
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DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
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RDMA0_SOUT_DSI2
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3,
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DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
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RDMA0_SOUT_DSI3
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DPI0
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
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DPI0_SEL_IN_RDMA1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
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DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DPI1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
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DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
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DPI1_SEL_IN_RDMA1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0,
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DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
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DSI0_SEL_IN_RDMA1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
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DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DSI1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
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DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
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DSI1_SEL_IN_RDMA1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
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DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DSI2
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
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DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
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DSI2_SEL_IN_RDMA1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
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DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DSI3
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
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DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
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DSI3_SEL_IN_RDMA1
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
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RDMA2_SOUT_DPI0
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
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DPI0_SEL_IN_RDMA2
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
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DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
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RDMA2_SOUT_DPI1
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
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DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
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DPI1_SEL_IN_RDMA2
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0,
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DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
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DSI0_SEL_IN_RDMA2
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
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DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
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RDMA2_SOUT_DSI1
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
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DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
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DSI1_SEL_IN_RDMA2
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
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DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
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RDMA2_SOUT_DSI2
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
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DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
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DSI2_SEL_IN_RDMA2
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
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DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
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RDMA2_SOUT_DSI3
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
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DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
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DSI3_SEL_IN_RDMA2
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}, {
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DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
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DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0,
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UFOE_MOUT_EN_DSI0
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}
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MMSYS_ROUTE(BLS, 0, DSI, 0,
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DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
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BLS_TO_DSI_RDMA1_TO_DPI1),
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MMSYS_ROUTE(BLS, 0, DSI, 0,
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DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
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DSI_SEL_IN_BLS),
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MMSYS_ROUTE(BLS, 0, DPI, 0,
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DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
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BLS_TO_DPI_RDMA1_TO_DSI),
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MMSYS_ROUTE(BLS, 0, DPI, 0,
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DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
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DSI_SEL_IN_RDMA),
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MMSYS_ROUTE(BLS, 0, DPI, 0,
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DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
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DPI_SEL_IN_BLS),
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MMSYS_ROUTE(GAMMA, 0, RDMA, 1,
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DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
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GAMMA_MOUT_EN_RDMA1),
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MMSYS_ROUTE(OD, 0, RDMA, 0,
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DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
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OD_MOUT_EN_RDMA0),
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MMSYS_ROUTE(OD, 1, RDMA, 1,
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DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
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OD1_MOUT_EN_RDMA1),
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MMSYS_ROUTE(OVL, 0, COLOR, 0,
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DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
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OVL0_MOUT_EN_COLOR0),
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MMSYS_ROUTE(OVL, 0, COLOR, 0,
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DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
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COLOR0_SEL_IN_OVL0),
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MMSYS_ROUTE(OVL, 0, RDMA, 0,
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DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
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OVL_MOUT_EN_RDMA),
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MMSYS_ROUTE(OVL, 1, COLOR, 1,
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DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
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OVL1_MOUT_EN_COLOR1),
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MMSYS_ROUTE(OVL, 1, COLOR, 1,
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DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
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COLOR1_SEL_IN_OVL1),
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MMSYS_ROUTE(RDMA, 0, DPI, 0,
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DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
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RDMA0_SOUT_DPI0),
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MMSYS_ROUTE(RDMA, 0, DPI, 1,
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DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
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RDMA0_SOUT_DPI1),
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MMSYS_ROUTE(RDMA, 0, DSI, 1,
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DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
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RDMA0_SOUT_DSI1),
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MMSYS_ROUTE(RDMA, 0, DSI, 2,
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DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
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RDMA0_SOUT_DSI2),
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MMSYS_ROUTE(RDMA, 0, DSI, 3,
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DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
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RDMA0_SOUT_DSI3),
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MMSYS_ROUTE(RDMA, 1, DPI, 0,
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DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DPI0),
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MMSYS_ROUTE(RDMA, 1, DPI, 0,
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DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
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DPI0_SEL_IN_RDMA1),
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MMSYS_ROUTE(RDMA, 1, DPI, 1,
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DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DPI1),
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MMSYS_ROUTE(RDMA, 1, DPI, 1,
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DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
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DPI1_SEL_IN_RDMA1),
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MMSYS_ROUTE(RDMA, 1, DSI, 0,
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DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
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DSI0_SEL_IN_RDMA1),
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MMSYS_ROUTE(RDMA, 1, DSI, 1,
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DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DSI1),
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MMSYS_ROUTE(RDMA, 1, DSI, 1,
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DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
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DSI1_SEL_IN_RDMA1),
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MMSYS_ROUTE(RDMA, 1, DSI, 2,
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DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DSI2),
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MMSYS_ROUTE(RDMA, 1, DSI, 2,
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DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
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DSI2_SEL_IN_RDMA1),
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MMSYS_ROUTE(RDMA, 1, DSI, 3,
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DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DSI3),
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MMSYS_ROUTE(RDMA, 1, DSI, 3,
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DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
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DSI3_SEL_IN_RDMA1),
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MMSYS_ROUTE(RDMA, 2, DPI, 0,
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DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
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RDMA2_SOUT_DPI0),
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MMSYS_ROUTE(RDMA, 2, DPI, 0,
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DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
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DPI0_SEL_IN_RDMA2),
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MMSYS_ROUTE(RDMA, 2, DPI, 1,
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DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
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RDMA2_SOUT_DPI1),
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MMSYS_ROUTE(RDMA, 2, DPI, 1,
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DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
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DPI1_SEL_IN_RDMA2),
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MMSYS_ROUTE(RDMA, 2, DSI, 0,
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DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
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DSI0_SEL_IN_RDMA2),
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MMSYS_ROUTE(RDMA, 2, DSI, 1,
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DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
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RDMA2_SOUT_DSI1),
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MMSYS_ROUTE(RDMA, 2, DSI, 1,
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DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
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DSI1_SEL_IN_RDMA2),
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MMSYS_ROUTE(RDMA, 2, DSI, 2,
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DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
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RDMA2_SOUT_DSI2),
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MMSYS_ROUTE(RDMA, 2, DSI, 2,
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DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
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DSI2_SEL_IN_RDMA2),
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};
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#endif /* __SOC_MEDIATEK_MTK_MMSYS_H */
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