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MIPS: Loongson64: Reorder CPUCFG model match arms

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Originally the match arms are ordered by model release date, however
the LOONGSON_64R cores are even more reduced capability-wise. So put
them at top of the switch block.

Suggested-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
WANG Xuerui 2020-05-30 15:32:43 +08:00 committed by Thomas Bogendoerfer
parent f06da27eb8
commit dd25ed7361
1 changed files with 16 additions and 16 deletions
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32
arch/mips/loongson64/cpucfg-emul.c
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@ -137,6 +137,22 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
/* Add CPUCFG features non-discoverable otherwise. */
switch (c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) {
case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
decode_loongson_config6(c);
probe_uca(c);
c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
LOONGSON_CFG1_TGTSYNC);
c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
LOONGSON_CFG2_LPM_REV2);
c->loongson3_cpucfg_data[2] = 0;
break;
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R1:
c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
@ -164,22 +180,6 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
LOONGSON_CFG3_LCAMVW_REV1);
break;
case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
decode_loongson_config6(c);
probe_uca(c);
c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
LOONGSON_CFG1_TGTSYNC);
c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
LOONGSON_CFG2_LPM_REV2);
c->loongson3_cpucfg_data[2] = 0;
break;
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0:
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_1:
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_0: