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thermal/drivers/renesas/rzg3e: Fix add thermal driver for the Renesas RZ/G3E SoC
When applied the change commit19d3a401a6, a conflict appeared resulting into a manual fix. However the new file rzg3e_thermal.c was not added but stayed locally in source tree and miss to be merged with the entire change. Fix this by adding the file back. Fixes:19d3a401a6("Add thermal driver for the Renesas RZ/G3E SoC") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202509272225.sARVqv2G-lkp@intel.com Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This commit is contained in:
John Madieu
Daniel Lezcano
parent
79428e6089
commit
dc67521c20
547
drivers/thermal/renesas/rzg3e_thermal.c
Normal file
547
drivers/thermal/renesas/rzg3e_thermal.c
Normal file
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@ -0,0 +1,547 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G3E TSU Temperature Sensor Unit
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*
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* Copyright (C) 2025 Renesas Electronics Corporation
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*/
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#include <linux/clk.h>
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#include <linux/cleanup.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/thermal.h>
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#include <linux/units.h>
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#include "../thermal_hwmon.h"
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/* TSU Register offsets and bits */
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#define TSU_SSUSR 0x00
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#define TSU_SSUSR_EN_TS BIT(0)
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#define TSU_SSUSR_ADC_PD_TS BIT(1)
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#define TSU_SSUSR_SOC_TS_EN BIT(2)
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#define TSU_STRGR 0x04
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#define TSU_STRGR_ADST BIT(0)
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#define TSU_SOSR1 0x08
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#define TSU_SOSR1_ADCT_8 0x03
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#define TSU_SOSR1_ADCS BIT(4)
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#define TSU_SOSR1_OUTSEL BIT(9)
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#define TSU_SCRR 0x10
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#define TSU_SCRR_OUT12BIT_TS GENMASK(11, 0)
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#define TSU_SSR 0x14
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#define TSU_SSR_CONV BIT(0)
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#define TSU_CMSR 0x18
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#define TSU_CMSR_CMPEN BIT(0)
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#define TSU_LLSR 0x1C
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#define TSU_ULSR 0x20
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#define TSU_SISR 0x30
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#define TSU_SISR_ADF BIT(0)
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#define TSU_SISR_CMPF BIT(1)
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#define TSU_SIER 0x34
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#define TSU_SIER_CMPIE BIT(1)
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#define TSU_SICR 0x38
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#define TSU_SICR_ADCLR BIT(0)
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#define TSU_SICR_CMPCLR BIT(1)
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/* Temperature calculation constants from datasheet */
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#define TSU_TEMP_D (-41)
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#define TSU_TEMP_E 126
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#define TSU_CODE_MAX 0xFFF
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/* Timing specifications from datasheet */
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#define TSU_POWERUP_TIME_US 120 /* 120T at 1MHz sensor clock per datasheet */
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#define TSU_CONV_TIME_US 50 /* Per sample conversion time */
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#define TSU_POLL_DELAY_US 10 /* Polling interval */
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#define TSU_MIN_CLOCK_RATE 24000000 /* TSU_PCLK minimum 24MHz */
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/**
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* struct rzg3e_thermal_priv - RZ/G3E TSU private data
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* @base: TSU register base
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* @dev: device pointer
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* @syscon: regmap for calibration values
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* @zone: thermal zone device
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* @rstc: reset control
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* @trmval0: calibration value 0 (b)
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* @trmval1: calibration value 1 (c)
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* @trim_offset: offset for trim registers in syscon
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* @lock: protects hardware access during conversions
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*/
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struct rzg3e_thermal_priv {
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void __iomem *base;
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struct device *dev;
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struct regmap *syscon;
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struct thermal_zone_device *zone;
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struct reset_control *rstc;
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u16 trmval0;
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u16 trmval1;
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u32 trim_offset;
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struct mutex lock;
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};
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static int rzg3e_thermal_power_on(struct rzg3e_thermal_priv *priv)
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{
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u32 val;
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int ret;
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/* Clear any pending interrupts */
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writel(TSU_SICR_ADCLR | TSU_SICR_CMPCLR, priv->base + TSU_SICR);
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/* Disable all interrupts during setup */
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writel(0, priv->base + TSU_SIER);
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/*
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* Power-on sequence per datasheet 7.11.9.1:
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* SOC_TS_EN must be set at same time or before EN_TS and ADC_PD_TS
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*/
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val = TSU_SSUSR_SOC_TS_EN | TSU_SSUSR_EN_TS;
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writel(val, priv->base + TSU_SSUSR);
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/* Wait for sensor stabilization per datasheet 7.11.7.1 */
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usleep_range(TSU_POWERUP_TIME_US, TSU_POWERUP_TIME_US + 10);
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/* Configure for average mode with 8 samples */
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val = TSU_SOSR1_OUTSEL | TSU_SOSR1_ADCT_8;
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writel(val, priv->base + TSU_SOSR1);
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/* Ensure we're in single scan mode (default) */
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val = readl(priv->base + TSU_SOSR1);
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if (val & TSU_SOSR1_ADCS) {
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dev_err(priv->dev, "Invalid scan mode setting\n");
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return -EINVAL;
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}
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/* Wait for any ongoing conversion to complete */
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ret = readl_poll_timeout(priv->base + TSU_SSR, val,
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!(val & TSU_SSR_CONV),
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TSU_POLL_DELAY_US,
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USEC_PER_MSEC);
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if (ret) {
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dev_err(priv->dev, "Timeout waiting for conversion\n");
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return ret;
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}
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return 0;
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}
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static void rzg3e_thermal_power_off(struct rzg3e_thermal_priv *priv)
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{
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/* Disable all interrupts */
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writel(0, priv->base + TSU_SIER);
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/* Clear pending interrupts */
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writel(TSU_SICR_ADCLR | TSU_SICR_CMPCLR, priv->base + TSU_SICR);
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/* Power down sequence per datasheet */
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writel(TSU_SSUSR_ADC_PD_TS, priv->base + TSU_SSUSR);
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}
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/*
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* Convert 12-bit sensor code to temperature in millicelsius
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* Formula from datasheet 7.11.7.8:
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* T(°C) = ((e - d) / (c - b)) * (a - b) + d
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* where: a = sensor code, b = trmval0, c = trmval1, d = -41, e = 126
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*/
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static int rzg3e_thermal_code_to_temp(struct rzg3e_thermal_priv *priv, u16 code)
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{
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int temp_e_mc = TSU_TEMP_E * MILLIDEGREE_PER_DEGREE;
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int temp_d_mc = TSU_TEMP_D * MILLIDEGREE_PER_DEGREE;
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s64 numerator, denominator;
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int temp_mc;
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numerator = (temp_e_mc - temp_d_mc) * (s64)(code - priv->trmval0);
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denominator = priv->trmval1 - priv->trmval0;
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temp_mc = div64_s64(numerator, denominator) + temp_d_mc;
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return clamp(temp_mc, temp_d_mc, temp_e_mc);
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}
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/*
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* Convert temperature in millicelsius to 12-bit sensor code
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* Formula from datasheet 7.11.7.9 (inverse of above)
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*/
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static u16 rzg3e_thermal_temp_to_code(struct rzg3e_thermal_priv *priv, int temp_mc)
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{
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int temp_e_mc = TSU_TEMP_E * MILLIDEGREE_PER_DEGREE;
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int temp_d_mc = TSU_TEMP_D * MILLIDEGREE_PER_DEGREE;
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s64 numerator, denominator;
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s64 code;
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numerator = (temp_mc - temp_d_mc) * (priv->trmval1 - priv->trmval0);
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denominator = temp_e_mc - temp_d_mc;
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code = div64_s64(numerator, denominator) + priv->trmval0;
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return clamp_val(code, 0, TSU_CODE_MAX);
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}
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static int rzg3e_thermal_get_temp(struct thermal_zone_device *tz, int *temp)
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{
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struct rzg3e_thermal_priv *priv = thermal_zone_device_priv(tz);
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u32 status, code;
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int ret, timeout;
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ret = pm_runtime_resume_and_get(priv->dev);
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if (ret < 0)
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return ret;
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guard(mutex)(&priv->lock);
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/* Clear any previous conversion status */
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writel(TSU_SICR_ADCLR, priv->base + TSU_SICR);
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/* Start single conversion */
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writel(TSU_STRGR_ADST, priv->base + TSU_STRGR);
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/* Wait for conversion completion - 8 samples at ~50us each */
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timeout = TSU_CONV_TIME_US * 8 * 2; /* Double for margin */
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ret = readl_poll_timeout(priv->base + TSU_SISR, status,
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status & TSU_SISR_ADF,
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TSU_POLL_DELAY_US, timeout);
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if (ret) {
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dev_err(priv->dev, "Conversion timeout (status=0x%08x)\n", status);
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goto out;
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}
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/* Read the averaged result and clear the complete flag */
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code = readl(priv->base + TSU_SCRR) & TSU_SCRR_OUT12BIT_TS;
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writel(TSU_SICR_ADCLR, priv->base + TSU_SICR);
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/* Convert to temperature */
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*temp = rzg3e_thermal_code_to_temp(priv, code);
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dev_dbg(priv->dev, "temp=%d mC (%d.%03d°C), code=0x%03x\n",
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*temp, *temp / 1000, abs(*temp) % 1000, code);
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out:
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pm_runtime_mark_last_busy(priv->dev);
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pm_runtime_put_autosuspend(priv->dev);
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return ret;
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}
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static int rzg3e_thermal_set_trips(struct thermal_zone_device *tz,
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int low, int high)
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{
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struct rzg3e_thermal_priv *priv = thermal_zone_device_priv(tz);
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u16 low_code, high_code;
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u32 val;
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int ret;
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/* Hardware requires low < high */
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if (low >= high)
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return -EINVAL;
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ret = pm_runtime_resume_and_get(priv->dev);
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if (ret < 0)
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return ret;
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guard(mutex)(&priv->lock);
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/* Convert temperatures to codes */
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low_code = rzg3e_thermal_temp_to_code(priv, low);
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high_code = rzg3e_thermal_temp_to_code(priv, high);
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dev_dbg(priv->dev, "set_trips: low=%d high=%d (codes: 0x%03x/0x%03x)\n",
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low, high, low_code, high_code);
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/* Disable comparison during reconfiguration */
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writel(0, priv->base + TSU_SIER);
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writel(0, priv->base + TSU_CMSR);
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/* Clear any pending comparison interrupts */
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writel(TSU_SICR_CMPCLR, priv->base + TSU_SICR);
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/* Set trip points */
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writel(low_code, priv->base + TSU_LLSR);
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writel(high_code, priv->base + TSU_ULSR);
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/*
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* Ensure OUTSEL is set for comparison per datasheet 7.11.7.4
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* Comparison uses averaged data
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*/
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val = readl(priv->base + TSU_SOSR1);
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val |= TSU_SOSR1_OUTSEL;
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writel(val, priv->base + TSU_SOSR1);
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/* Enable comparison with "out of range" mode (CMPCOND=0) */
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writel(TSU_CMSR_CMPEN, priv->base + TSU_CMSR);
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/* Unmask compare IRQ and start a conversion to evaluate window */
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writel(TSU_SIER_CMPIE, priv->base + TSU_SIER);
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writel(TSU_STRGR_ADST, priv->base + TSU_STRGR);
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pm_runtime_mark_last_busy(priv->dev);
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pm_runtime_put_autosuspend(priv->dev);
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return 0;
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}
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static irqreturn_t rzg3e_thermal_irq_thread(int irq, void *data)
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{
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struct rzg3e_thermal_priv *priv = data;
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dev_dbg(priv->dev, "Temperature threshold crossed\n");
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/* Notify thermal framework to re-evaluate trip points */
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thermal_zone_device_update(priv->zone, THERMAL_TRIP_VIOLATED);
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return IRQ_HANDLED;
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}
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static irqreturn_t rzg3e_thermal_irq(int irq, void *data)
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{
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struct rzg3e_thermal_priv *priv = data;
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u32 status;
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status = readl(priv->base + TSU_SISR);
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/* Check if comparison interrupt occurred */
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if (status & TSU_SISR_CMPF) {
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/* Clear irq flag and disable interrupt until reconfigured */
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writel(TSU_SICR_CMPCLR, priv->base + TSU_SICR);
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writel(0, priv->base + TSU_SIER);
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return IRQ_WAKE_THREAD;
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}
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return IRQ_NONE;
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}
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static const struct thermal_zone_device_ops rzg3e_tz_ops = {
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.get_temp = rzg3e_thermal_get_temp,
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.set_trips = rzg3e_thermal_set_trips,
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};
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static int rzg3e_thermal_get_calibration(struct rzg3e_thermal_priv *priv)
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{
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u32 val;
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int ret;
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/* Read calibration values from syscon */
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ret = regmap_read(priv->syscon, priv->trim_offset, &val);
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if (ret)
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return ret;
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priv->trmval0 = val & GENMASK(11, 0);
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ret = regmap_read(priv->syscon, priv->trim_offset + 4, &val);
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if (ret)
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return ret;
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priv->trmval1 = val & GENMASK(11, 0);
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/* Validate calibration data */
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if (!priv->trmval0 || !priv->trmval1 ||
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priv->trmval0 == priv->trmval1 ||
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priv->trmval0 == 0xFFF || priv->trmval1 == 0xFFF) {
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dev_err(priv->dev, "Invalid calibration: b=0x%03x, c=0x%03x\n",
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priv->trmval0, priv->trmval1);
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return -EINVAL;
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}
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dev_dbg(priv->dev, "Calibration: b=0x%03x (%u), c=0x%03x (%u)\n",
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priv->trmval0, priv->trmval0, priv->trmval1, priv->trmval1);
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return 0;
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}
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static int rzg3e_thermal_parse_dt(struct rzg3e_thermal_priv *priv)
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{
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struct device_node *np = priv->dev->of_node;
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u32 offset;
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priv->syscon = syscon_regmap_lookup_by_phandle_args(np, "renesas,tsu-trim", 1, &offset);
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if (IS_ERR(priv->syscon))
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return dev_err_probe(priv->dev, PTR_ERR(priv->syscon),
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"Failed to parse renesas,tsu-trim\n");
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priv->trim_offset = offset;
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return 0;
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}
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static int rzg3e_thermal_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rzg3e_thermal_priv *priv;
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struct clk *clk;
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int irq, ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = dev;
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ret = devm_mutex_init(dev, &priv->lock);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, priv);
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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/* Parse device tree for trim register info */
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ret = rzg3e_thermal_parse_dt(priv);
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if (ret)
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return ret;
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/* Get clock to verify frequency - clock is managed by power domain */
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clk = devm_clk_get(dev, NULL);
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if (IS_ERR(clk))
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return dev_err_probe(dev, PTR_ERR(clk),
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"Failed to get clock\n");
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if (clk_get_rate(clk) < TSU_MIN_CLOCK_RATE)
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return dev_err_probe(dev, -EINVAL,
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"Clock rate %lu Hz too low (min %u Hz)\n",
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clk_get_rate(clk), TSU_MIN_CLOCK_RATE);
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priv->rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL);
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if (IS_ERR(priv->rstc))
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return dev_err_probe(dev, PTR_ERR(priv->rstc),
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"Failed to get/deassert reset control\n");
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/* Get calibration data */
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ret = rzg3e_thermal_get_calibration(priv);
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if (ret)
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return dev_err_probe(dev, ret,
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"Failed to get valid calibration data\n");
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/* Get comparison interrupt */
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irq = platform_get_irq_byname(pdev, "adcmpi");
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||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
/* Enable runtime PM */
|
||||
pm_runtime_set_autosuspend_delay(dev, 1000);
|
||||
pm_runtime_use_autosuspend(dev);
|
||||
devm_pm_runtime_enable(dev);
|
||||
|
||||
/* Initial hardware setup */
|
||||
ret = pm_runtime_resume_and_get(dev);
|
||||
if (ret < 0)
|
||||
return dev_err_probe(dev, ret, "Runtime resume failed\n");
|
||||
|
||||
/* Register thermal zone - this will trigger DT parsing */
|
||||
priv->zone = devm_thermal_of_zone_register(dev, 0, priv, &rzg3e_tz_ops);
|
||||
if (IS_ERR(priv->zone)) {
|
||||
ret = PTR_ERR(priv->zone);
|
||||
dev_err(dev, "Failed to register thermal zone: %d\n", ret);
|
||||
goto err_pm_put;
|
||||
}
|
||||
|
||||
/* Request threaded IRQ for comparison interrupt */
|
||||
ret = devm_request_threaded_irq(dev, irq, rzg3e_thermal_irq,
|
||||
rzg3e_thermal_irq_thread,
|
||||
IRQF_ONESHOT, "rzg3e_thermal", priv);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to request IRQ: %d\n", ret);
|
||||
goto err_pm_put;
|
||||
}
|
||||
|
||||
/* Add hwmon sysfs interface */
|
||||
ret = devm_thermal_add_hwmon_sysfs(dev, priv->zone);
|
||||
if (ret)
|
||||
dev_warn(dev, "Failed to add hwmon sysfs attributes\n");
|
||||
|
||||
pm_runtime_mark_last_busy(dev);
|
||||
pm_runtime_put_autosuspend(dev);
|
||||
|
||||
dev_info(dev, "RZ/G3E thermal sensor registered\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err_pm_put:
|
||||
pm_runtime_put_sync(dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rzg3e_thermal_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
|
||||
|
||||
rzg3e_thermal_power_off(priv);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzg3e_thermal_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
|
||||
|
||||
return rzg3e_thermal_power_on(priv);
|
||||
}
|
||||
|
||||
static int rzg3e_thermal_suspend(struct device *dev)
|
||||
{
|
||||
struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
|
||||
|
||||
/* If device is active, power it off */
|
||||
if (pm_runtime_active(dev))
|
||||
rzg3e_thermal_power_off(priv);
|
||||
|
||||
/* Assert reset to ensure clean state after resume */
|
||||
reset_control_assert(priv->rstc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzg3e_thermal_resume(struct device *dev)
|
||||
{
|
||||
struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
/* Deassert reset */
|
||||
ret = reset_control_deassert(priv->rstc);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to deassert reset: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* If device was active before suspend, power it back on */
|
||||
if (pm_runtime_active(dev))
|
||||
return rzg3e_thermal_power_on(priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops rzg3e_thermal_pm_ops = {
|
||||
RUNTIME_PM_OPS(rzg3e_thermal_runtime_suspend,
|
||||
rzg3e_thermal_runtime_resume, NULL)
|
||||
SYSTEM_SLEEP_PM_OPS(rzg3e_thermal_suspend, rzg3e_thermal_resume)
|
||||
};
|
||||
|
||||
static const struct of_device_id rzg3e_thermal_dt_ids[] = {
|
||||
{ .compatible = "renesas,r9a09g047-tsu" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rzg3e_thermal_dt_ids);
|
||||
|
||||
static struct platform_driver rzg3e_thermal_driver = {
|
||||
.driver = {
|
||||
.name = "rzg3e_thermal",
|
||||
.of_match_table = rzg3e_thermal_dt_ids,
|
||||
.pm = pm_ptr(&rzg3e_thermal_pm_ops),
|
||||
},
|
||||
.probe = rzg3e_thermal_probe,
|
||||
};
|
||||
module_platform_driver(rzg3e_thermal_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Renesas RZ/G3E TSU Thermal Sensor Driver");
|
||||
MODULE_AUTHOR("John Madieu <john.madieu.xa@bp.renesas.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user