From b6bd4d1a5b6c46be32bbe0d3447de59f8a5885e0 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 2 Jul 2026 20:11:16 +0100 Subject: [PATCH 01/14] arm64: Don't number registers in cpu-feature-registers.rst cpu-feature-regsters.rst documents the set of userspace visible ID registers. At present the section for each register is numbered, this has lead to the registers being documented in a haphazard order as new ones have been added to the end of the list to avoid renumbering. Remove the numbers so we can avoid this problem in future. Signed-off-by: Mark Brown Signed-off-by: Will Deacon --- .../arch/arm64/cpu-feature-registers.rst | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst index add66afc7b03..c6e5bc053c09 100644 --- a/Documentation/arch/arm64/cpu-feature-registers.rst +++ b/Documentation/arch/arm64/cpu-feature-registers.rst @@ -113,7 +113,7 @@ infrastructure: 4. List of registers with visible features ------------------------------------------- - 1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0 + ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0 +------------------------------+---------+---------+ | Name | bits | visible | @@ -146,7 +146,7 @@ infrastructure: +------------------------------+---------+---------+ - 2) ID_AA64PFR0_EL1 - Processor Feature Register 0 + ID_AA64PFR0_EL1 - Processor Feature Register 0 +------------------------------+---------+---------+ | Name | bits | visible | @@ -173,7 +173,7 @@ infrastructure: +------------------------------+---------+---------+ - 3) ID_AA64PFR1_EL1 - Processor Feature Register 1 + ID_AA64PFR1_EL1 - Processor Feature Register 1 +------------------------------+---------+---------+ | Name | bits | visible | @@ -188,7 +188,7 @@ infrastructure: +------------------------------+---------+---------+ - 4) MIDR_EL1 - Main ID Register + MIDR_EL1 - Main ID Register +------------------------------+---------+---------+ | Name | bits | visible | @@ -208,7 +208,7 @@ infrastructure: as available on the CPU where it is fetched and is not a system wide safe value. - 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 + ID_AA64ISAR1_EL1 - Instruction set attribute register 1 +------------------------------+---------+---------+ | Name | bits | visible | @@ -240,7 +240,7 @@ infrastructure: | DPB | [3-0] | y | +------------------------------+---------+---------+ - 6) ID_AA64MMFR0_EL1 - Memory model feature register 0 + ID_AA64MMFR0_EL1 - Memory model feature register 0 +------------------------------+---------+---------+ | Name | bits | visible | @@ -248,7 +248,7 @@ infrastructure: | ECV | [63-60] | y | +------------------------------+---------+---------+ - 7) ID_AA64MMFR2_EL1 - Memory model feature register 2 + ID_AA64MMFR2_EL1 - Memory model feature register 2 +------------------------------+---------+---------+ | Name | bits | visible | @@ -256,7 +256,7 @@ infrastructure: | AT | [35-32] | y | +------------------------------+---------+---------+ - 8) ID_AA64ZFR0_EL1 - SVE feature ID register 0 + ID_AA64ZFR0_EL1 - SVE feature ID register 0 +------------------------------+---------+---------+ | Name | bits | visible | @@ -282,7 +282,7 @@ infrastructure: | SVEVer | [3-0] | y | +------------------------------+---------+---------+ - 8) ID_AA64MMFR1_EL1 - Memory model feature register 1 + ID_AA64MMFR1_EL1 - Memory model feature register 1 +------------------------------+---------+---------+ | Name | bits | visible | @@ -290,7 +290,7 @@ infrastructure: | AFP | [47-44] | y | +------------------------------+---------+---------+ - 9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2 + ID_AA64ISAR2_EL1 - Instruction set attribute register 2 +------------------------------+---------+---------+ | Name | bits | visible | @@ -312,7 +312,7 @@ infrastructure: | WFXT | [3-0] | y | +------------------------------+---------+---------+ - 10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 + MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 +------------------------------+---------+---------+ | Name | bits | visible | @@ -320,7 +320,7 @@ infrastructure: | FPDP | [11-8] | y | +------------------------------+---------+---------+ - 11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1 + MVFR1_EL1 - AArch32 Media and VFP Feature Register 1 +------------------------------+---------+---------+ | Name | bits | visible | @@ -334,7 +334,7 @@ infrastructure: | SIMDLS | [11-8] | y | +------------------------------+---------+---------+ - 12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5 + ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5 +------------------------------+---------+---------+ | Name | bits | visible | From 4788adeca0e03cc34d0846a25f3d028ab75eadd1 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 2 Jul 2026 20:11:17 +0100 Subject: [PATCH 02/14] arm64: Document missing bitfields in cpu-feature-registers.rst We have been rather lax in updating the list of visible bitfields in the ID registers in cpu-feature-registers.rst, it is currently missing several of the registers and quite a few bitfields in existing registers. Bring it into sync with current -next. Signed-off-by: Mark Brown Signed-off-by: Will Deacon --- .../arch/arm64/cpu-feature-registers.rst | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst index c6e5bc053c09..4b10980d4a40 100644 --- a/Documentation/arch/arm64/cpu-feature-registers.rst +++ b/Documentation/arch/arm64/cpu-feature-registers.rst @@ -113,6 +113,30 @@ infrastructure: 4. List of registers with visible features ------------------------------------------- + ID_AA64FPFR0_EL1 - Floating Point feature ID register 0 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | F8CVT | [31] | y | + +------------------------------+---------+---------+ + | F8FMA | [30] | y | + +------------------------------+---------+---------+ + | F8DP4 | [29] | y | + +------------------------------+---------+---------+ + | F8DP2 | [28] | y | + +------------------------------+---------+---------+ + | F8MM8 | [27] | y | + +------------------------------+---------+---------+ + | F8MM4 | [26] | y | + +------------------------------+---------+---------+ + | F16MM2 | [15] | y | + +------------------------------+---------+---------+ + | F8E4M3 | [1] | y | + +------------------------------+---------+---------+ + | F8E5M2 | [0] | y | + +------------------------------+---------+---------+ + ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0 +------------------------------+---------+---------+ @@ -178,6 +202,8 @@ infrastructure: +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ + | GCS | [47-44] | y | + +------------------------------+---------+---------+ | SME | [27-24] | y | +------------------------------+---------+---------+ | MTE | [11-8] | y | @@ -187,6 +213,17 @@ infrastructure: | BT | [3-0] | y | +------------------------------+---------+---------+ + ID_AA64PFR2_EL1 - Processor Feature Register 2 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | FPMR | [35-32] | y | + +------------------------------+---------+---------+ + | MTEFAR | [11-8] | y | + +------------------------------+---------+---------+ + | MTESTOREONLY | [7-4] | y | + +------------------------------+---------+---------+ MIDR_EL1 - Main ID Register @@ -213,6 +250,8 @@ infrastructure: +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ + | LS64 | [63-60] | y | + +------------------------------+---------+---------+ | I8MM | [55-52] | y | +------------------------------+---------+---------+ | DGH | [51-48] | y | @@ -256,6 +295,68 @@ infrastructure: | AT | [35-32] | y | +------------------------------+---------+---------+ + ID_AA64MMFR3_EL1 - Memory model feature register 3 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | S1POE | [19-16] | y | + +------------------------------+---------+---------+ + + ID_AA64SMFR0_EL1 - SME feature ID register 0 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | FA64 | [63] | y | + +------------------------------+---------+---------+ + | LUT6 | [61] | y | + +------------------------------+---------+---------+ + | LUTv2 | [60] | y | + +------------------------------+---------+---------+ + | SMEver | [59-56] | y | + +------------------------------+---------+---------+ + | I16I64 | [55-52] | y | + +------------------------------+---------+---------+ + | F64F64 | [48] | y | + +------------------------------+---------+---------+ + | I16I32 | [47-44] | y | + +------------------------------+---------+---------+ + | B16B16 | [43] | y | + +------------------------------+---------+---------+ + | F16F16 | [42] | y | + +------------------------------+---------+---------+ + | F8F16 | [41] | y | + +------------------------------+---------+---------+ + | F8F32 | [40] | y | + +------------------------------+---------+---------+ + | I8I32 | [39-36] | y | + +------------------------------+---------+---------+ + | F16F32 | [35] | y | + +------------------------------+---------+---------+ + | B16F32 | [34] | y | + +------------------------------+---------+---------+ + | BI32I32 | [33] | y | + +------------------------------+---------+---------+ + | F32F32 | [32] | y | + +------------------------------+---------+---------+ + | SF8FMA | [30] | y | + +------------------------------+---------+---------+ + | SF8DP4 | [29] | y | + +------------------------------+---------+---------+ + | SF8DP2 | [28] | y | + +------------------------------+---------+---------+ + | SBitPerm | [25] | y | + +------------------------------+---------+---------+ + | AES | [24] | y | + +------------------------------+---------+---------+ + | SFEXPA | [23] | y | + +------------------------------+---------+---------+ + | STMOP | [16] | y | + +------------------------------+---------+---------+ + | SMOP4 | [0] | y | + +------------------------------+---------+---------+ + ID_AA64ZFR0_EL1 - SVE feature ID register 0 +------------------------------+---------+---------+ @@ -265,6 +366,8 @@ infrastructure: +------------------------------+---------+---------+ | F32MM | [55-52] | y | +------------------------------+---------+---------+ + | F16MM | [51-48] | y | + +------------------------------+---------+---------+ | I8MM | [47-44] | y | +------------------------------+---------+---------+ | SM4 | [43-40] | y | @@ -277,6 +380,8 @@ infrastructure: +------------------------------+---------+---------+ | BitPerm | [19-16] | y | +------------------------------+---------+---------+ + | EltPerm | [15-12] | y | + +------------------------------+---------+---------+ | AES | [7-4] | y | +------------------------------+---------+---------+ | SVEVer | [3-0] | y | @@ -295,6 +400,8 @@ infrastructure: +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ + | LUT | [59-56] | y | + +------------------------------+---------+---------+ | CSSC | [55-52] | y | +------------------------------+---------+---------+ | RPRFM | [51-48] | y | @@ -312,6 +419,18 @@ infrastructure: | WFXT | [3-0] | y | +------------------------------+---------+---------+ + ID_AA64ISAR3_EL1 - Instruction set attribute register 3 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | FPRCVT | [31-28] | y | + +------------------------------+---------+---------+ + | LSFE | [19-16] | y | + +------------------------------+---------+---------+ + | FAMINMAX | [7-4] | y | + +------------------------------+---------+---------+ + MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 +------------------------------+---------+---------+ @@ -327,6 +446,10 @@ infrastructure: +------------------------------+---------+---------+ | SIMDFMAC | [31-28] | y | +------------------------------+---------+---------+ + | FPHP | [27-24] | y | + +------------------------------+---------+---------+ + | SIMDHP | [23-20] | y | + +------------------------------+---------+---------+ | SIMDSP | [19-16] | y | +------------------------------+---------+---------+ | SIMDInt | [15-12] | y | @@ -348,6 +471,29 @@ infrastructure: | AES | [7-4] | y | +------------------------------+---------+---------+ + ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | I8MM | [27-24] | y | + +------------------------------+---------+---------+ + | BF16 | [23-20] | y | + +------------------------------+---------+---------+ + | SB | [15-12] | y | + +------------------------------+---------+---------+ + | FHM | [11-8] | y | + +------------------------------+---------+---------+ + | DP | [7-4] | y | + +------------------------------+---------+---------+ + + ID_PFR2_EL1 - AArch32 Processor Feature Register 2 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | SSBS | [7-4] | y | + +------------------------------+---------+---------+ Appendix I: Example ------------------- From 21a2ca869edd51373e3a953641ee97efee5c0557 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 2 Jul 2026 20:11:18 +0100 Subject: [PATCH 03/14] arm64: Sort registers in cpu-feature-registers.rst In order to make it a bit easier to work with sort the list of registers in cpu-feature-registers.rst lexically. There should be no content changes resulting from this patch. Signed-off-by: Mark Brown Signed-off-by: Will Deacon --- .../arch/arm64/cpu-feature-registers.rst | 297 +++++++++--------- 1 file changed, 149 insertions(+), 148 deletions(-) diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst index 4b10980d4a40..683bdd90c705 100644 --- a/Documentation/arch/arm64/cpu-feature-registers.rst +++ b/Documentation/arch/arm64/cpu-feature-registers.rst @@ -170,6 +170,108 @@ infrastructure: +------------------------------+---------+---------+ + ID_AA64ISAR1_EL1 - Instruction set attribute register 1 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | LS64 | [63-60] | y | + +------------------------------+---------+---------+ + | I8MM | [55-52] | y | + +------------------------------+---------+---------+ + | DGH | [51-48] | y | + +------------------------------+---------+---------+ + | BF16 | [47-44] | y | + +------------------------------+---------+---------+ + | SB | [39-36] | y | + +------------------------------+---------+---------+ + | FRINTTS | [35-32] | y | + +------------------------------+---------+---------+ + | GPI | [31-28] | y | + +------------------------------+---------+---------+ + | GPA | [27-24] | y | + +------------------------------+---------+---------+ + | LRCPC | [23-20] | y | + +------------------------------+---------+---------+ + | FCMA | [19-16] | y | + +------------------------------+---------+---------+ + | JSCVT | [15-12] | y | + +------------------------------+---------+---------+ + | API | [11-8] | y | + +------------------------------+---------+---------+ + | APA | [7-4] | y | + +------------------------------+---------+---------+ + | DPB | [3-0] | y | + +------------------------------+---------+---------+ + + ID_AA64ISAR2_EL1 - Instruction set attribute register 2 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | LUT | [59-56] | y | + +------------------------------+---------+---------+ + | CSSC | [55-52] | y | + +------------------------------+---------+---------+ + | RPRFM | [51-48] | y | + +------------------------------+---------+---------+ + | BC | [23-20] | y | + +------------------------------+---------+---------+ + | MOPS | [19-16] | y | + +------------------------------+---------+---------+ + | APA3 | [15-12] | y | + +------------------------------+---------+---------+ + | GPA3 | [11-8] | y | + +------------------------------+---------+---------+ + | RPRES | [7-4] | y | + +------------------------------+---------+---------+ + | WFXT | [3-0] | y | + +------------------------------+---------+---------+ + + ID_AA64ISAR3_EL1 - Instruction set attribute register 3 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | FPRCVT | [31-28] | y | + +------------------------------+---------+---------+ + | LSFE | [19-16] | y | + +------------------------------+---------+---------+ + | FAMINMAX | [7-4] | y | + +------------------------------+---------+---------+ + + ID_AA64MMFR0_EL1 - Memory model feature register 0 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | ECV | [63-60] | y | + +------------------------------+---------+---------+ + + ID_AA64MMFR1_EL1 - Memory model feature register 1 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | AFP | [47-44] | y | + +------------------------------+---------+---------+ + + ID_AA64MMFR2_EL1 - Memory model feature register 2 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | AT | [35-32] | y | + +------------------------------+---------+---------+ + + ID_AA64MMFR3_EL1 - Memory model feature register 3 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | S1POE | [19-16] | y | + +------------------------------+---------+---------+ + ID_AA64PFR0_EL1 - Processor Feature Register 0 +------------------------------+---------+---------+ @@ -225,84 +327,6 @@ infrastructure: | MTESTOREONLY | [7-4] | y | +------------------------------+---------+---------+ - MIDR_EL1 - Main ID Register - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | Implementer | [31-24] | y | - +------------------------------+---------+---------+ - | Variant | [23-20] | y | - +------------------------------+---------+---------+ - | Architecture | [19-16] | y | - +------------------------------+---------+---------+ - | PartNum | [15-4] | y | - +------------------------------+---------+---------+ - | Revision | [3-0] | y | - +------------------------------+---------+---------+ - - NOTE: The 'visible' fields of MIDR_EL1 will contain the value - as available on the CPU where it is fetched and is not a system - wide safe value. - - ID_AA64ISAR1_EL1 - Instruction set attribute register 1 - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | LS64 | [63-60] | y | - +------------------------------+---------+---------+ - | I8MM | [55-52] | y | - +------------------------------+---------+---------+ - | DGH | [51-48] | y | - +------------------------------+---------+---------+ - | BF16 | [47-44] | y | - +------------------------------+---------+---------+ - | SB | [39-36] | y | - +------------------------------+---------+---------+ - | FRINTTS | [35-32] | y | - +------------------------------+---------+---------+ - | GPI | [31-28] | y | - +------------------------------+---------+---------+ - | GPA | [27-24] | y | - +------------------------------+---------+---------+ - | LRCPC | [23-20] | y | - +------------------------------+---------+---------+ - | FCMA | [19-16] | y | - +------------------------------+---------+---------+ - | JSCVT | [15-12] | y | - +------------------------------+---------+---------+ - | API | [11-8] | y | - +------------------------------+---------+---------+ - | APA | [7-4] | y | - +------------------------------+---------+---------+ - | DPB | [3-0] | y | - +------------------------------+---------+---------+ - - ID_AA64MMFR0_EL1 - Memory model feature register 0 - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | ECV | [63-60] | y | - +------------------------------+---------+---------+ - - ID_AA64MMFR2_EL1 - Memory model feature register 2 - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | AT | [35-32] | y | - +------------------------------+---------+---------+ - - ID_AA64MMFR3_EL1 - Memory model feature register 3 - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | S1POE | [19-16] | y | - +------------------------------+---------+---------+ - ID_AA64SMFR0_EL1 - SME feature ID register 0 +------------------------------+---------+---------+ @@ -387,76 +411,6 @@ infrastructure: | SVEVer | [3-0] | y | +------------------------------+---------+---------+ - ID_AA64MMFR1_EL1 - Memory model feature register 1 - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | AFP | [47-44] | y | - +------------------------------+---------+---------+ - - ID_AA64ISAR2_EL1 - Instruction set attribute register 2 - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | LUT | [59-56] | y | - +------------------------------+---------+---------+ - | CSSC | [55-52] | y | - +------------------------------+---------+---------+ - | RPRFM | [51-48] | y | - +------------------------------+---------+---------+ - | BC | [23-20] | y | - +------------------------------+---------+---------+ - | MOPS | [19-16] | y | - +------------------------------+---------+---------+ - | APA3 | [15-12] | y | - +------------------------------+---------+---------+ - | GPA3 | [11-8] | y | - +------------------------------+---------+---------+ - | RPRES | [7-4] | y | - +------------------------------+---------+---------+ - | WFXT | [3-0] | y | - +------------------------------+---------+---------+ - - ID_AA64ISAR3_EL1 - Instruction set attribute register 3 - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | FPRCVT | [31-28] | y | - +------------------------------+---------+---------+ - | LSFE | [19-16] | y | - +------------------------------+---------+---------+ - | FAMINMAX | [7-4] | y | - +------------------------------+---------+---------+ - - MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | FPDP | [11-8] | y | - +------------------------------+---------+---------+ - - MVFR1_EL1 - AArch32 Media and VFP Feature Register 1 - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | SIMDFMAC | [31-28] | y | - +------------------------------+---------+---------+ - | FPHP | [27-24] | y | - +------------------------------+---------+---------+ - | SIMDHP | [23-20] | y | - +------------------------------+---------+---------+ - | SIMDSP | [19-16] | y | - +------------------------------+---------+---------+ - | SIMDInt | [15-12] | y | - +------------------------------+---------+---------+ - | SIMDLS | [11-8] | y | - +------------------------------+---------+---------+ - ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5 +------------------------------+---------+---------+ @@ -495,6 +449,53 @@ infrastructure: | SSBS | [7-4] | y | +------------------------------+---------+---------+ + MIDR_EL1 - Main ID Register + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | Implementer | [31-24] | y | + +------------------------------+---------+---------+ + | Variant | [23-20] | y | + +------------------------------+---------+---------+ + | Architecture | [19-16] | y | + +------------------------------+---------+---------+ + | PartNum | [15-4] | y | + +------------------------------+---------+---------+ + | Revision | [3-0] | y | + +------------------------------+---------+---------+ + + NOTE: The 'visible' fields of MIDR_EL1 will contain the value + as available on the CPU where it is fetched and is not a system + wide safe value. + + MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | FPDP | [11-8] | y | + +------------------------------+---------+---------+ + + MVFR1_EL1 - AArch32 Media and VFP Feature Register 1 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | SIMDFMAC | [31-28] | y | + +------------------------------+---------+---------+ + | FPHP | [27-24] | y | + +------------------------------+---------+---------+ + | SIMDHP | [23-20] | y | + +------------------------------+---------+---------+ + | SIMDSP | [19-16] | y | + +------------------------------+---------+---------+ + | SIMDInt | [15-12] | y | + +------------------------------+---------+---------+ + | SIMDLS | [11-8] | y | + +------------------------------+---------+---------+ + + Appendix I: Example ------------------- From bc7f7ddc64df4b821d7dce97db58c5bf84e0efd1 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 2 Jul 2026 20:11:19 +0100 Subject: [PATCH 04/14] arm64: Remove hidden bitfields from cpu-feature-registers.rst We currently have a visibility column in the tables for the registers in cpu-feature-registers.rst but this is always "y" for every register other than ID_AA64PFR0_EL1. Given that the documentation of the full set of bitfields is readily available in the architecture documentation it is redundant for us to explicitly document things we don't advertise, and the kernel documentation will inevitably lag the architecture. Just remove the visibility column and hidden bitfields. Signed-off-by: Mark Brown Signed-off-by: Will Deacon --- .../arch/arm64/cpu-feature-registers.rst | 618 +++++++++--------- 1 file changed, 303 insertions(+), 315 deletions(-) diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst index 683bdd90c705..fc63ccb666bf 100644 --- a/Documentation/arch/arm64/cpu-feature-registers.rst +++ b/Documentation/arch/arm64/cpu-feature-registers.rst @@ -115,355 +115,343 @@ infrastructure: ID_AA64FPFR0_EL1 - Floating Point feature ID register 0 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | F8CVT | [31] | y | - +------------------------------+---------+---------+ - | F8FMA | [30] | y | - +------------------------------+---------+---------+ - | F8DP4 | [29] | y | - +------------------------------+---------+---------+ - | F8DP2 | [28] | y | - +------------------------------+---------+---------+ - | F8MM8 | [27] | y | - +------------------------------+---------+---------+ - | F8MM4 | [26] | y | - +------------------------------+---------+---------+ - | F16MM2 | [15] | y | - +------------------------------+---------+---------+ - | F8E4M3 | [1] | y | - +------------------------------+---------+---------+ - | F8E5M2 | [0] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | F8CVT | [31] | + +------------------------------+---------+ + | F8FMA | [30] | + +------------------------------+---------+ + | F8DP4 | [29] | + +------------------------------+---------+ + | F8DP2 | [28] | + +------------------------------+---------+ + | F8MM8 | [27] | + +------------------------------+---------+ + | F8MM4 | [26] | + +------------------------------+---------+ + | F16MM2 | [15] | + +------------------------------+---------+ + | F8E4M3 | [1] | + +------------------------------+---------+ + | F8E5M2 | [0] | + +------------------------------+---------+ ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | RNDR | [63-60] | y | - +------------------------------+---------+---------+ - | TS | [55-52] | y | - +------------------------------+---------+---------+ - | FHM | [51-48] | y | - +------------------------------+---------+---------+ - | DP | [47-44] | y | - +------------------------------+---------+---------+ - | SM4 | [43-40] | y | - +------------------------------+---------+---------+ - | SM3 | [39-36] | y | - +------------------------------+---------+---------+ - | SHA3 | [35-32] | y | - +------------------------------+---------+---------+ - | RDM | [31-28] | y | - +------------------------------+---------+---------+ - | ATOMICS | [23-20] | y | - +------------------------------+---------+---------+ - | CRC32 | [19-16] | y | - +------------------------------+---------+---------+ - | SHA2 | [15-12] | y | - +------------------------------+---------+---------+ - | SHA1 | [11-8] | y | - +------------------------------+---------+---------+ - | AES | [7-4] | y | + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | RNDR | [63-60] | + +------------------------------+---------+ + | TS | [55-52] | + +------------------------------+---------+ + | FHM | [51-48] | + +------------------------------+---------+ + | DP | [47-44] | + +------------------------------+---------+ + | SM4 | [43-40] | + +------------------------------+---------+ + | SM3 | [39-36] | + +------------------------------+---------+ + | SHA3 | [35-32] | + +------------------------------+---------+ + | RDM | [31-28] | + +------------------------------+---------+ + | ATOMICS | [23-20] | + +------------------------------+---------+ + | CRC32 | [19-16] | + +------------------------------+---------+ + | SHA2 | [15-12] | + +------------------------------+---------+ + | SHA1 | [11-8] | + +------------------------------+---------+ + | AES | [7-4] | +------------------------------+---------+---------+ ID_AA64ISAR1_EL1 - Instruction set attribute register 1 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | LS64 | [63-60] | y | - +------------------------------+---------+---------+ - | I8MM | [55-52] | y | - +------------------------------+---------+---------+ - | DGH | [51-48] | y | - +------------------------------+---------+---------+ - | BF16 | [47-44] | y | - +------------------------------+---------+---------+ - | SB | [39-36] | y | - +------------------------------+---------+---------+ - | FRINTTS | [35-32] | y | - +------------------------------+---------+---------+ - | GPI | [31-28] | y | - +------------------------------+---------+---------+ - | GPA | [27-24] | y | - +------------------------------+---------+---------+ - | LRCPC | [23-20] | y | - +------------------------------+---------+---------+ - | FCMA | [19-16] | y | - +------------------------------+---------+---------+ - | JSCVT | [15-12] | y | - +------------------------------+---------+---------+ - | API | [11-8] | y | - +------------------------------+---------+---------+ - | APA | [7-4] | y | - +------------------------------+---------+---------+ - | DPB | [3-0] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | LS64 | [63-60] | + +------------------------------+---------+ + | I8MM | [55-52] | + +------------------------------+---------+ + | DGH | [51-48] | + +------------------------------+---------+ + | BF16 | [47-44] | + +------------------------------+---------+ + | SB | [39-36] | + +------------------------------+---------+ + | FRINTTS | [35-32] | + +------------------------------+---------+ + | GPI | [31-28] | + +------------------------------+---------+ + | GPA | [27-24] | + +------------------------------+---------+ + | LRCPC | [23-20] | + +------------------------------+---------+ + | FCMA | [19-16] | + +------------------------------+---------+ + | JSCVT | [15-12] | + +------------------------------+---------+ + | API | [11-8] | + +------------------------------+---------+ + | APA | [7-4] | + +------------------------------+---------+ + | DPB | [3-0] | + +------------------------------+---------+ ID_AA64ISAR2_EL1 - Instruction set attribute register 2 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | LUT | [59-56] | y | - +------------------------------+---------+---------+ - | CSSC | [55-52] | y | - +------------------------------+---------+---------+ - | RPRFM | [51-48] | y | - +------------------------------+---------+---------+ - | BC | [23-20] | y | - +------------------------------+---------+---------+ - | MOPS | [19-16] | y | - +------------------------------+---------+---------+ - | APA3 | [15-12] | y | - +------------------------------+---------+---------+ - | GPA3 | [11-8] | y | - +------------------------------+---------+---------+ - | RPRES | [7-4] | y | - +------------------------------+---------+---------+ - | WFXT | [3-0] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | LUT | [59-56] | + +------------------------------+---------+ + | CSSC | [55-52] | + +------------------------------+---------+ + | RPRFM | [51-48] | + +------------------------------+---------+ + | BC | [23-20] | + +------------------------------+---------+ + | MOPS | [19-16] | + +------------------------------+---------+ + | APA3 | [15-12] | + +------------------------------+---------+ + | GPA3 | [11-8] | + +------------------------------+---------+ + | RPRES | [7-4] | + +------------------------------+---------+ + | WFXT | [3-0] | + +------------------------------+---------+ ID_AA64ISAR3_EL1 - Instruction set attribute register 3 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | FPRCVT | [31-28] | y | - +------------------------------+---------+---------+ - | LSFE | [19-16] | y | - +------------------------------+---------+---------+ - | FAMINMAX | [7-4] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | FPRCVT | [31-28] | + +------------------------------+---------+ + | LSFE | [19-16] | + +------------------------------+---------+ + | FAMINMAX | [7-4] | + +------------------------------+---------+ ID_AA64MMFR0_EL1 - Memory model feature register 0 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | ECV | [63-60] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | ECV | [63-60] | + +------------------------------+---------+ ID_AA64MMFR1_EL1 - Memory model feature register 1 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | AFP | [47-44] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | AFP | [47-44] | + +------------------------------+---------+ ID_AA64MMFR2_EL1 - Memory model feature register 2 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | AT | [35-32] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | AT | [35-32] | + +------------------------------+---------+ ID_AA64MMFR3_EL1 - Memory model feature register 3 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | S1POE | [19-16] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | S1POE | [19-16] | + +------------------------------+---------+ ID_AA64PFR0_EL1 - Processor Feature Register 0 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | DIT | [51-48] | y | - +------------------------------+---------+---------+ - | MPAM | [43-40] | n | - +------------------------------+---------+---------+ - | SVE | [35-32] | y | - +------------------------------+---------+---------+ - | GIC | [27-24] | n | - +------------------------------+---------+---------+ - | AdvSIMD | [23-20] | y | - +------------------------------+---------+---------+ - | FP | [19-16] | y | - +------------------------------+---------+---------+ - | EL3 | [15-12] | n | - +------------------------------+---------+---------+ - | EL2 | [11-8] | n | - +------------------------------+---------+---------+ - | EL1 | [7-4] | n | - +------------------------------+---------+---------+ - | EL0 | [3-0] | n | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | DIT | [51-48] | + +------------------------------+---------+ + | SVE | [35-32] | + +------------------------------+---------+ + | AdvSIMD | [23-20] | + +------------------------------+---------+ + | FP | [19-16] | + +------------------------------+---------+ ID_AA64PFR1_EL1 - Processor Feature Register 1 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | GCS | [47-44] | y | - +------------------------------+---------+---------+ - | SME | [27-24] | y | - +------------------------------+---------+---------+ - | MTE | [11-8] | y | - +------------------------------+---------+---------+ - | SSBS | [7-4] | y | - +------------------------------+---------+---------+ - | BT | [3-0] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | GCS | [47-44] | + +------------------------------+---------+ + | SME | [27-24] | + +------------------------------+---------+ + | MTE | [11-8] | + +------------------------------+---------+ + | SSBS | [7-4] | + +------------------------------+---------+ + | BT | [3-0] | + +------------------------------+---------+ ID_AA64PFR2_EL1 - Processor Feature Register 2 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | FPMR | [35-32] | y | - +------------------------------+---------+---------+ - | MTEFAR | [11-8] | y | - +------------------------------+---------+---------+ - | MTESTOREONLY | [7-4] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | FPMR | [35-32] | + +------------------------------+---------+ + | MTEFAR | [11-8] | + +------------------------------+---------+ + | MTESTOREONLY | [7-4] | + +------------------------------+---------+ ID_AA64SMFR0_EL1 - SME feature ID register 0 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | FA64 | [63] | y | - +------------------------------+---------+---------+ - | LUT6 | [61] | y | - +------------------------------+---------+---------+ - | LUTv2 | [60] | y | - +------------------------------+---------+---------+ - | SMEver | [59-56] | y | - +------------------------------+---------+---------+ - | I16I64 | [55-52] | y | - +------------------------------+---------+---------+ - | F64F64 | [48] | y | - +------------------------------+---------+---------+ - | I16I32 | [47-44] | y | - +------------------------------+---------+---------+ - | B16B16 | [43] | y | - +------------------------------+---------+---------+ - | F16F16 | [42] | y | - +------------------------------+---------+---------+ - | F8F16 | [41] | y | - +------------------------------+---------+---------+ - | F8F32 | [40] | y | - +------------------------------+---------+---------+ - | I8I32 | [39-36] | y | - +------------------------------+---------+---------+ - | F16F32 | [35] | y | - +------------------------------+---------+---------+ - | B16F32 | [34] | y | - +------------------------------+---------+---------+ - | BI32I32 | [33] | y | - +------------------------------+---------+---------+ - | F32F32 | [32] | y | - +------------------------------+---------+---------+ - | SF8FMA | [30] | y | - +------------------------------+---------+---------+ - | SF8DP4 | [29] | y | - +------------------------------+---------+---------+ - | SF8DP2 | [28] | y | - +------------------------------+---------+---------+ - | SBitPerm | [25] | y | - +------------------------------+---------+---------+ - | AES | [24] | y | - +------------------------------+---------+---------+ - | SFEXPA | [23] | y | - +------------------------------+---------+---------+ - | STMOP | [16] | y | - +------------------------------+---------+---------+ - | SMOP4 | [0] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | FA64 | [63] | + +------------------------------+---------+ + | LUT6 | [61] | + +------------------------------+---------+ + | LUTv2 | [60] | + +------------------------------+---------+ + | SMEver | [59-56] | + +------------------------------+---------+ + | I16I64 | [55-52] | + +------------------------------+---------+ + | F64F64 | [48] | + +------------------------------+---------+ + | I16I32 | [47-44] | + +------------------------------+---------+ + | B16B16 | [43] | + +------------------------------+---------+ + | F16F16 | [42] | + +------------------------------+---------+ + | F8F16 | [41] | + +------------------------------+---------+ + | F8F32 | [40] | + +------------------------------+---------+ + | I8I32 | [39-36] | + +------------------------------+---------+ + | F16F32 | [35] | + +------------------------------+---------+ + | B16F32 | [34] | + +------------------------------+---------+ + | BI32I32 | [33] | + +------------------------------+---------+ + | F32F32 | [32] | + +------------------------------+---------+ + | SF8FMA | [30] | + +------------------------------+---------+ + | SF8DP4 | [29] | + +------------------------------+---------+ + | SF8DP2 | [28] | + +------------------------------+---------+ + | SBitPerm | [25] | + +------------------------------+---------+ + | AES | [24] | + +------------------------------+---------+ + | SFEXPA | [23] | + +------------------------------+---------+ + | STMOP | [16] | + +------------------------------+---------+ + | SMOP4 | [0] | + +------------------------------+---------+ ID_AA64ZFR0_EL1 - SVE feature ID register 0 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | F64MM | [59-56] | y | - +------------------------------+---------+---------+ - | F32MM | [55-52] | y | - +------------------------------+---------+---------+ - | F16MM | [51-48] | y | - +------------------------------+---------+---------+ - | I8MM | [47-44] | y | - +------------------------------+---------+---------+ - | SM4 | [43-40] | y | - +------------------------------+---------+---------+ - | SHA3 | [35-32] | y | - +------------------------------+---------+---------+ - | B16B16 | [27-24] | y | - +------------------------------+---------+---------+ - | BF16 | [23-20] | y | - +------------------------------+---------+---------+ - | BitPerm | [19-16] | y | - +------------------------------+---------+---------+ - | EltPerm | [15-12] | y | - +------------------------------+---------+---------+ - | AES | [7-4] | y | - +------------------------------+---------+---------+ - | SVEVer | [3-0] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | F64MM | [59-56] | + +------------------------------+---------+ + | F32MM | [55-52] | + +------------------------------+---------+ + | F16MM | [51-48] | + +------------------------------+---------+ + | I8MM | [47-44] | + +------------------------------+---------+ + | SM4 | [43-40] | + +------------------------------+---------+ + | SHA3 | [35-32] | + +------------------------------+---------+ + | B16B16 | [27-24] | + +------------------------------+---------+ + | BF16 | [23-20] | + +------------------------------+---------+ + | BitPerm | [19-16] | + +------------------------------+---------+ + | EltPerm | [15-12] | + +------------------------------+---------+ + | AES | [7-4] | + +------------------------------+---------+ + | SVEVer | [3-0] | + +------------------------------+---------+ ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | CRC32 | [19-16] | y | - +------------------------------+---------+---------+ - | SHA2 | [15-12] | y | - +------------------------------+---------+---------+ - | SHA1 | [11-8] | y | - +------------------------------+---------+---------+ - | AES | [7-4] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | CRC32 | [19-16] | + +------------------------------+---------+ + | SHA2 | [15-12] | + +------------------------------+---------+ + | SHA1 | [11-8] | + +------------------------------+---------+ + | AES | [7-4] | + +------------------------------+---------+ ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | I8MM | [27-24] | y | - +------------------------------+---------+---------+ - | BF16 | [23-20] | y | - +------------------------------+---------+---------+ - | SB | [15-12] | y | - +------------------------------+---------+---------+ - | FHM | [11-8] | y | - +------------------------------+---------+---------+ - | DP | [7-4] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | I8MM | [27-24] | + +------------------------------+---------+ + | BF16 | [23-20] | + +------------------------------+---------+ + | SB | [15-12] | + +------------------------------+---------+ + | FHM | [11-8] | + +------------------------------+---------+ + | DP | [7-4] | + +------------------------------+---------+ ID_PFR2_EL1 - AArch32 Processor Feature Register 2 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | SSBS | [7-4] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | SSBS | [7-4] | + +------------------------------+---------+ MIDR_EL1 - Main ID Register - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | Implementer | [31-24] | y | - +------------------------------+---------+---------+ - | Variant | [23-20] | y | - +------------------------------+---------+---------+ - | Architecture | [19-16] | y | - +------------------------------+---------+---------+ - | PartNum | [15-4] | y | - +------------------------------+---------+---------+ - | Revision | [3-0] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | Implementer | [31-24] | + +------------------------------+---------+ + | Variant | [23-20] | + +------------------------------+---------+ + | Architecture | [19-16] | + +------------------------------+---------+ + | PartNum | [15-4] | + +------------------------------+---------+ + | Revision | [3-0] | + +------------------------------+---------+ NOTE: The 'visible' fields of MIDR_EL1 will contain the value as available on the CPU where it is fetched and is not a system @@ -471,29 +459,29 @@ infrastructure: MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | FPDP | [11-8] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | FPDP | [11-8] | + +------------------------------+---------+ MVFR1_EL1 - AArch32 Media and VFP Feature Register 1 - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | SIMDFMAC | [31-28] | y | - +------------------------------+---------+---------+ - | FPHP | [27-24] | y | - +------------------------------+---------+---------+ - | SIMDHP | [23-20] | y | - +------------------------------+---------+---------+ - | SIMDSP | [19-16] | y | - +------------------------------+---------+---------+ - | SIMDInt | [15-12] | y | - +------------------------------+---------+---------+ - | SIMDLS | [11-8] | y | - +------------------------------+---------+---------+ + +------------------------------+---------+ + | Name | bits | + +------------------------------+---------+ + | SIMDFMAC | [31-28] | + +------------------------------+---------+ + | FPHP | [27-24] | + +------------------------------+---------+ + | SIMDHP | [23-20] | + +------------------------------+---------+ + | SIMDSP | [19-16] | + +------------------------------+---------+ + | SIMDInt | [15-12] | + +------------------------------+---------+ + | SIMDLS | [11-8] | + +------------------------------+---------+ Appendix I: Example From d50a908ffde534596107072c4897cf17c5ccd9e5 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 26 Jul 2026 17:10:02 -0700 Subject: [PATCH 05/14] arm64: fix cpu-feature-registers Malformed table The "visible" column was dropped so that last line's extra pieces should also be dropped to prevent a docs build error: Documentation/arch/arm64/cpu-feature-registers.rst:170: ERROR: Malformed table. Right border not aligned or missing. +------------------------------+---------+ | Name | bits | +------------------------------+---------+ | RNDR | [63-60] | +------------------------------+---------+ | TS | [55-52] | +------------------------------+---------+ ... +------------------------------+---------+ | AES | [7-4] | +------------------------------+---------+---------+ [docutils] Fixes: bc7f7ddc64df ("arm64: Remove hidden bitfields from cpu-feature-registers.rst") Signed-off-by: Randy Dunlap Signed-off-by: Will Deacon --- Documentation/arch/arm64/cpu-feature-registers.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst index fc63ccb666bf..f603afe323d6 100644 --- a/Documentation/arch/arm64/cpu-feature-registers.rst +++ b/Documentation/arch/arm64/cpu-feature-registers.rst @@ -167,7 +167,7 @@ infrastructure: | SHA1 | [11-8] | +------------------------------+---------+ | AES | [7-4] | - +------------------------------+---------+---------+ + +------------------------------+---------+ ID_AA64ISAR1_EL1 - Instruction set attribute register 1 From 6c74dcb1e1b73b381950f8991fa7493bdefbf3c9 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Thu, 30 Jul 2026 14:27:57 +0100 Subject: [PATCH 06/14] arm64: cpucaps: Remove stale comment about keeping capabilities sorted There is no functional requirement to keep the entries in arm64's tools/cpucaps file sorted alphabetically and, in fact, they have fallen out of order over time. Given that only the arm64 tree touches this file and the perceived benefit of sorting was to help with conflicts, just remove the stale comment and accept that we're collectively not very good at the alphabet. In the limited cases where a specific ordering is important, we enforce it through build-time assertions (e.g. in can_use_gic_priorities()). Cc: Catalin Marinas Acked-by: Mark Rutland Reviewed-by: Fuad Tabba Reported-by: Marc Zyngier Acked-by: Marc Zyngier Signed-off-by: Will Deacon --- arch/arm64/tools/cpucaps | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 9b85a84f6fd4..3fcac789b0a4 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 # -# Internal CPU capabilities constants, keep this list sorted +# Internal CPU capabilities constants ALWAYS_BOOT ALWAYS_SYSTEM From 482145e0327f46f5051dfa2da4254867039928b2 Mon Sep 17 00:00:00 2001 From: Linu Cherian Date: Thu, 23 Jul 2026 10:10:28 +0530 Subject: [PATCH 07/14] arm64: cputype: Add Cortex-A520AE definitions Add cputype definitions for Cortex-A520AE. The definition can be found in Cortex-A520AE TRM, https://developer.arm.com/documentation/107726/0001/ as part of MIDR_EL1 bit descriptions. This is going to be used in the bbml3 support list. Reviewed-by: Gavin Shan Reviewed-by: Anshuman Khandual Signed-off-by: Linu Cherian Signed-off-by: Will Deacon --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 1b9f0cda1336..e41fae46426b 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -82,6 +82,7 @@ #define ARM_CPU_PART_CORTEX_X1 0xD44 #define ARM_CPU_PART_CORTEX_A510 0xD46 #define ARM_CPU_PART_CORTEX_A520 0xD80 +#define ARM_CPU_PART_CORTEX_A520AE 0xD88 #define ARM_CPU_PART_CORTEX_A710 0xD47 #define ARM_CPU_PART_CORTEX_A715 0xD4D #define ARM_CPU_PART_CORTEX_X2 0xD48 @@ -176,6 +177,7 @@ #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) #define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520) +#define MIDR_CORTEX_A520AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520AE) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715) #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) From 357230cb5276b0d224327ae2bb372d13f2243320 Mon Sep 17 00:00:00 2001 From: Linu Cherian Date: Thu, 23 Jul 2026 10:10:29 +0530 Subject: [PATCH 08/14] arm64: cputype: Add C1-Nano definitions Add cputype definitions for C1-Nano. The definition can be found in C1-Nano TRM, https://developer.arm.com/documentation/107753/0002 as part of MIDR_EL1 bit descriptions. This is going to be used in the bbml3 support list. Reviewed-by: Gavin Shan Reviewed-by: Anshuman Khandual Signed-off-by: Linu Cherian Signed-off-by: Will Deacon --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index e41fae46426b..1fa29616e586 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -100,6 +100,7 @@ #define ARM_CPU_PART_CORTEX_A720AE 0xD89 #define ARM_CPU_PART_C1_ULTRA 0xD8C #define ARM_CPU_PART_NEOVERSE_N3 0xD8E +#define ARM_CPU_PART_C1_NANO 0xD8A #define ARM_CPU_PART_C1_PRO 0xD8B #define ARM_CPU_PART_C1_PREMIUM 0xD90 @@ -195,6 +196,7 @@ #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE) #define MIDR_C1_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_ULTRA) #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3) +#define MIDR_C1_NANO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_NANO) #define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO) #define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PREMIUM) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) From a7ac60414475fdd811575e45ffc45e1f59e404b3 Mon Sep 17 00:00:00 2001 From: Linu Cherian Date: Thu, 23 Jul 2026 10:10:30 +0530 Subject: [PATCH 09/14] arm64: cpufeature: Extend bbml2_noabort support list Add below cpus to the midr list, which supports BBML2_NOABORT. Cortex A520(AE) Cortex A715 Cortex A720(AE) Cortex A725 Neoverse N3 C1-Nano C1-Pro C1-Ultra C1-Premium C1-Ultra and C1-Premium both suffer from erratum 3683289, where Break-Before-Make must be followed to avoid a livelock. For both CPUs, the erratum is fixed from r1p1. Hence we do not enable BBML2_NOABORT for CPU revisions <= r1p0. The relevant SDENs are: * C1-Ultra: https://developer.arm.com/documentation/111077/9-00/ * C1-Premium: https://developer.arm.com/documentation/111078/9-00/ Reviewed-by: Gavin Shan Reviewed-by: Anshuman Khandual Signed-off-by: Linu Cherian Signed-off-by: Will Deacon --- Documentation/arch/arm64/silicon-errata.rst | 4 ++++ arch/arm64/kernel/cpufeature.c | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index 014aa1c215a1..57c778446936 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -242,10 +242,14 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-V3AE | #4193784 | ARM64_ERRATUM_4118414 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | C1-Premium | #3683289 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | C1-Premium | #4193780 | ARM64_ERRATUM_4118414 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | C1-Pro | #4193714 | ARM64_ERRATUM_4193714 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | C1-Ultra | #3683289 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | C1-Ultra | #4193780 | ARM64_ERRATUM_4118414 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | MMU-500 | #562869, | ARM_SMMU_MMU_500_CPRE_ERRATA| diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9a22df0c5120..98d2cfc2dc90 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2152,6 +2152,16 @@ bool cpu_supports_bbml2_noabort(void) MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), MIDR_ALL_VERSIONS(MIDR_AMPERE1), MIDR_ALL_VERSIONS(MIDR_AMPERE1A), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), + MIDR_ALL_VERSIONS(MIDR_C1_NANO), + MIDR_ALL_VERSIONS(MIDR_C1_PRO), + /* Erratum 3683289 fixed in r1p1 */ + MIDR_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf, 0xf), + MIDR_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf, 0xf), {} }; From e4fa246243083391a65a721dbbc340766668d829 Mon Sep 17 00:00:00 2001 From: Linu Cherian Date: Thu, 23 Jul 2026 10:10:31 +0530 Subject: [PATCH 10/14] arm64: sysreg: Add BBM_3 Add BBM_3 definition for ID_AA64MMFR2_EL1 register. Reviewed-by: Gavin Shan Reviewed-by: Anshuman Khandual Signed-off-by: Linu Cherian Signed-off-by: Will Deacon --- arch/arm64/tools/sysreg | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 7cb61aca3797..e070ada06196 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2259,6 +2259,7 @@ UnsignedEnum 55:52 BBM 0b0000 0 0b0001 1 0b0010 2 + 0b0011 3 EndEnum UnsignedEnum 51:48 TTL 0b0000 NI From 94104e3cfa8036ac2457aa0c2ca1351e16d77159 Mon Sep 17 00:00:00 2001 From: Linu Cherian Date: Thu, 23 Jul 2026 10:10:32 +0530 Subject: [PATCH 11/14] arm64: cpufeature: Rename BBML2_NOABORT as BBML3 - As bbml2_noabort is functionally equivalent to bbml3, rename cpu/system_supports_bbml2_noabort to cpu/system_supports_bbml3. The ARM64 capability name is also renamed accordingly. - As BBML2_NOABORT or the equivalent BBML3 is the kernel requirement for setting up linear map with block/contpte mappings and not BBML2, replace all bbml2 references with bbml3. FEAT_BBML3, is introduced as part of 2025 Architecture Extensions. https://developer.arm.com/documentation/109697/2026_03/2025-Architecture-Extensions No functional changes are introduced with this patch. Reviewed-by: Gavin Shan Reviewed-by: Anshuman Khandual Signed-off-by: Linu Cherian Signed-off-by: Will Deacon --- arch/arm64/include/asm/cpufeature.h | 6 ++-- arch/arm64/kernel/cpufeature.c | 30 +++++----------- arch/arm64/mm/contpte.c | 21 +++++------ arch/arm64/mm/mmu.c | 54 ++++++++++++++--------------- arch/arm64/mm/proc.S | 4 +-- arch/arm64/tools/cpucaps | 2 +- 6 files changed, 50 insertions(+), 67 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index a57870fa96db..d90040fb9de6 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -878,11 +878,11 @@ static inline bool system_supports_pmuv3(void) return cpus_have_final_cap(ARM64_HAS_PMUV3); } -bool cpu_supports_bbml2_noabort(void); +bool cpu_supports_bbml3(void); -static inline bool system_supports_bbml2_noabort(void) +static inline bool system_supports_bbml3(void) { - return alternative_has_cap_unlikely(ARM64_HAS_BBML2_NOABORT); + return alternative_has_cap_unlikely(ARM64_HAS_BBML3); } int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 98d2cfc2dc90..896bafdb00b1 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2131,21 +2131,10 @@ static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); } -bool cpu_supports_bbml2_noabort(void) +bool cpu_supports_bbml3(void) { - /* - * We want to allow usage of BBML2 in as wide a range of kernel contexts - * as possible. This list is therefore an allow-list of known-good - * implementations that both support BBML2 and additionally, fulfill the - * extra constraint of never generating TLB conflict aborts when using - * the relaxed BBML2 semantics (such aborts make use of BBML2 in certain - * kernel contexts difficult to prove safe against recursive aborts). - * - * Note that implementations can only be considered "known-good" if their - * implementors attest to the fact that the implementation never raises - * TLB conflict aborts for BBML2 mapping granularity changes. - */ - static const struct midr_range supports_bbml2_noabort_list[] = { + /* CPUs that support BBML3 but dont advertise through ID_AA64MMFR2_EL1 */ + static const struct midr_range supports_bbml3_list[] = { MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf), @@ -2165,8 +2154,7 @@ bool cpu_supports_bbml2_noabort(void) {} }; - /* Does our cpu guarantee to never raise TLB conflict aborts? */ - if (!is_midr_in_range_list(supports_bbml2_noabort_list)) + if (!is_midr_in_range_list(supports_bbml3_list)) return false; /* @@ -2177,9 +2165,9 @@ bool cpu_supports_bbml2_noabort(void) return true; } -static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int scope) +static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope) { - return cpu_supports_bbml2_noabort(); + return cpu_supports_bbml3(); } static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) @@ -3072,10 +3060,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = { ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) }, { - .desc = "BBM Level 2 without TLB conflict abort", - .capability = ARM64_HAS_BBML2_NOABORT, + .desc = "BBM Level 3", + .capability = ARM64_HAS_BBML3, .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, - .matches = has_bbml2_noabort, + .matches = has_bbml3, }, { .desc = "52-bit Virtual Addressing for KVM (LPA2)", diff --git a/arch/arm64/mm/contpte.c b/arch/arm64/mm/contpte.c index 2de12656b4d8..0acab179fc1a 100644 --- a/arch/arm64/mm/contpte.c +++ b/arch/arm64/mm/contpte.c @@ -89,7 +89,7 @@ static void contpte_convert(struct mm_struct *mm, unsigned long addr, } /* - * On eliding the __tlb_flush_range() under BBML2+noabort: + * On eliding the __tlb_flush_range() under BBML3: * * NOTE: Instead of using N=16 as the contiguous block length, we use * N=4 for clarity. @@ -135,7 +135,7 @@ static void contpte_convert(struct mm_struct *mm, unsigned long addr, * contiguous TLB entry, which is a micro-optimisation opportunity, * but does not affect correctness. * - * In the BBML2 case, the change is avoiding the intermediate tlbi+dsb. + * In the BBML3 case, the change is avoiding the intermediate tlbi+dsb. * This means a few things, but notably other PEs will still "see" any * stale cached TLB entries. This could lead to a "contiguous bit * misprogramming" issue until the final tlbi+dsb of the changed page, @@ -158,21 +158,16 @@ static void contpte_convert(struct mm_struct *mm, unsigned long addr, * are present, and a write is made to this address, do we fault or * is the write permitted (via amalgamation)? * - * The relevant Arm ARM DDI 0487L.a requirements are RNGLXZ and RJQQTC, - * and together state that when BBML1 or BBML2 are implemented, either - * a TLB conflict abort is raised (which we expressly forbid), or will - * "produce an OA, access permissions, and memory attributes that are - * consistent with any of the programmed translation table values". - * - * That is to say, will either raise a TLB conflict, or produce one of - * the cached TLB entries, but never amalgamate. + * With BBML3 implemented, no TLB conflict abort is raised and the OA, + * access permissions and memory attributes produced is one of the cached + * TLB entries, but never amalgamate. * * Thus, as the page tables are only considered "consistent" after * the final tlbi+dsb (which evicts both the single stale (RW,n) TLB * entry as well as the new contiguous (RO,c) TLB entry), omitting the * initial tlbi+dsb is correct. * - * It is also important to note that at the end of the BBML2 folding + * It is also important to note that at the end of the BBML3 folding * case, we are still left with potentially all N TLB entries still * cached (the N-1 non-contiguous ptes, and the single contiguous * block). However, over time, natural TLB pressure will cause the @@ -214,7 +209,7 @@ static void contpte_convert(struct mm_struct *mm, unsigned long addr, * * |____| <--- tlbi + dsb * - * For BBML2, we again remove the intermediate tlbi+dsb. Here, there + * For BBML3, we again remove the intermediate tlbi+dsb. Here, there * are no issues, as the final tlbi+dsb covering the changed page is * guaranteed to remove the original large contiguous (RW,c) TLB entry, * as well as the intermediate (RW,n) TLB entry; the next access will @@ -224,7 +219,7 @@ static void contpte_convert(struct mm_struct *mm, unsigned long addr, * regardless. */ - if (!system_supports_bbml2_noabort()) + if (!system_supports_bbml3()) __flush_tlb_range(&vma, start_addr, addr, PAGE_SIZE, 3, TLBF_NOWALKCACHE); diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index a25d8beacc83..fad71d6bff40 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -779,18 +779,18 @@ static int split_kernel_leaf_mapping_locked(unsigned long addr) static inline bool force_pte_mapping(void) { - const bool bbml2 = system_capabilities_finalized() ? - system_supports_bbml2_noabort() : cpu_supports_bbml2_noabort(); + const bool bbml3 = system_capabilities_finalized() ? + system_supports_bbml3() : cpu_supports_bbml3(); if (debug_pagealloc_enabled()) return true; - if (bbml2) + if (bbml3) return false; return rodata_full || arm64_kfence_can_set_direct_map() || is_realm_world(); } static DEFINE_MUTEX(pgtable_split_lock); -static bool linear_map_requires_bbml2; +static bool linear_map_requires_bbml3; int split_kernel_leaf_mapping(unsigned long start, unsigned long end) { @@ -803,15 +803,15 @@ int split_kernel_leaf_mapping(unsigned long start, unsigned long end) * always pte-mapped), we must not go any further because taking the * mutex below may sleep. Do not call force_pte_mapping() here because * it could return a confusing result if called from a secondary cpu - * prior to finalizing caps. Instead, linear_map_requires_bbml2 gives us + * prior to finalizing caps. Instead, linear_map_requires_bbml3 gives us * what we need. */ - if (!linear_map_requires_bbml2 || is_kfence_address((void *)start)) + if (!linear_map_requires_bbml3 || is_kfence_address((void *)start)) return 0; - if (!system_supports_bbml2_noabort()) { + if (!system_supports_bbml3()) { /* - * !BBML2_NOABORT systems should not be trying to change + * BBML3 systems should not be trying to change * permissions on anything that is not pte-mapped in the first * place. Just return early and let the permission change code * raise a warning if not already pte-mapped. @@ -828,8 +828,8 @@ int split_kernel_leaf_mapping(unsigned long start, unsigned long end) /* * Boot-time: Started secondary cpus but don't know if they - * support BBML2_NOABORT yet. Can't allow splitting in this - * window in case they don't. + * support BBML3 yet. Can't allow splitting in this window + * in case they don't. */ if (WARN_ON(num_online_cpus() > 1)) return -EBUSY; @@ -934,11 +934,11 @@ static int range_split_to_ptes(unsigned long start, unsigned long end, gfp_t gfp return ret; } -u32 idmap_kpti_bbml2_flag; +u32 idmap_kpti_bbml3_flag; -static void __init init_idmap_kpti_bbml2_flag(void) +static void __init init_idmap_kpti_bbml3_flag(void) { - WRITE_ONCE(idmap_kpti_bbml2_flag, 1); + WRITE_ONCE(idmap_kpti_bbml3_flag, 1); /* Must be visible to other CPUs before stop_machine() is called. */ smp_mb(); } @@ -947,7 +947,7 @@ static int __init linear_map_split_to_ptes(void *__unused) { /* * Repainting the linear map must be done by CPU0 (the boot CPU) because - * that's the only CPU that we know supports BBML2. The other CPUs will + * that's the only CPU that we know supports BBML3. The other CPUs will * be held in a waiting area with the idmap active. */ if (!smp_processor_id()) { @@ -960,7 +960,7 @@ static int __init linear_map_split_to_ptes(void *__unused) /* * Wait for all secondary CPUs to be put into the waiting area. */ - smp_cond_load_acquire(&idmap_kpti_bbml2_flag, VAL == num_online_cpus()); + smp_cond_load_acquire(&idmap_kpti_bbml3_flag, VAL == num_online_cpus()); /* * Walk all of the linear map [lstart, lend), except the kernel @@ -979,7 +979,7 @@ static int __init linear_map_split_to_ptes(void *__unused) * Relies on dsb in flush_tlb_kernel_range() to avoid reordering * before any page table split operations. */ - WRITE_ONCE(idmap_kpti_bbml2_flag, 0); + WRITE_ONCE(idmap_kpti_bbml3_flag, 0); } else { typedef void (wait_split_fn)(void); extern wait_split_fn wait_linear_map_split_to_ptes; @@ -988,7 +988,7 @@ static int __init linear_map_split_to_ptes(void *__unused) wait_fn = (void *)__pa_symbol(wait_linear_map_split_to_ptes); /* - * At least one secondary CPU doesn't support BBML2 so cannot + * At least one secondary CPU doesn't support BBML3 so cannot * tolerate the size of the live mappings changing. So have the * secondary CPUs wait for the boot CPU to make the changes * with the idmap active and init_mm inactive. @@ -1003,8 +1003,8 @@ static int __init linear_map_split_to_ptes(void *__unused) void __init linear_map_maybe_split_to_ptes(void) { - if (linear_map_requires_bbml2 && !system_supports_bbml2_noabort()) { - init_idmap_kpti_bbml2_flag(); + if (linear_map_requires_bbml3 && !system_supports_bbml3()) { + init_idmap_kpti_bbml3_flag(); stop_machine(linear_map_split_to_ptes, NULL, cpu_online_mask); } } @@ -1127,7 +1127,7 @@ bool arch_kfence_init_pool(void) mutex_unlock(&pgtable_split_lock); /* - * Since the system supports bbml2_noabort, tlb invalidation is not + * Since the system supports bbml3, tlb invalidation is not * required here; the pgtable mappings have been split to pte but larger * entries may safely linger in the TLB. */ @@ -1166,7 +1166,7 @@ static void __init map_mem(void) arm64_kfence_map_pool(); - linear_map_requires_bbml2 = !force_pte_mapping() && can_set_direct_map(); + linear_map_requires_bbml3 = !force_pte_mapping() && can_set_direct_map(); if (force_pte_mapping()) flags |= NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; @@ -1333,7 +1333,7 @@ void __init kpti_install_ng_mappings(void) if (arm64_use_ng_mappings) return; - init_idmap_kpti_bbml2_flag(); + init_idmap_kpti_bbml3_flag(); stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); } @@ -1394,7 +1394,7 @@ void __pi_map_range(phys_addr_t *pte, u64 start, u64 end, phys_addr_t pa, u64 va_offset); static u8 idmap_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __ro_after_init, - kpti_bbml2_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __ro_after_init; + kpti_bbml3_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __ro_after_init; static void __init create_idmap(void) { @@ -1406,17 +1406,17 @@ static void __init create_idmap(void) IDMAP_ROOT_LEVEL, (pte_t *)idmap_pg_dir, false, __phys_to_virt(ptep) - ptep); - if (linear_map_requires_bbml2 || + if (linear_map_requires_bbml3 || (IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0) && !arm64_use_ng_mappings)) { - phys_addr_t pa = __pa_symbol(&idmap_kpti_bbml2_flag); + phys_addr_t pa = __pa_symbol(&idmap_kpti_bbml3_flag); /* * The KPTI G-to-nG conversion code needs a read-write mapping * of its synchronization flag in the ID map. This is also used * when splitting the linear map to ptes if a secondary CPU - * doesn't support bbml2. + * doesn't support bbml3. */ - ptep = __pa_symbol(kpti_bbml2_ptes); + ptep = __pa_symbol(kpti_bbml3_ptes); __pi_map_range(&ptep, pa, pa + sizeof(u32), pa, PAGE_KERNEL, IDMAP_ROOT_LEVEL, (pte_t *)idmap_pg_dir, false, __phys_to_virt(ptep) - ptep); diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 22866b49be37..f4e4e71a0ea8 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -287,7 +287,7 @@ SYM_TYPED_FUNC_START(idmap_kpti_install_ng_mappings) mov x5, x3 // preserve temp_pte arg mrs swapper_ttb, ttbr1_el1 - adr_l flag_ptr, idmap_kpti_bbml2_flag + adr_l flag_ptr, idmap_kpti_bbml3_flag cbnz cpu, __idmap_kpti_secondary @@ -445,7 +445,7 @@ SYM_TYPED_FUNC_START(wait_linear_map_split_to_ptes) flag_ptr .req x4 mrs swapper_ttb, ttbr1_el1 - adr_l flag_ptr, idmap_kpti_bbml2_flag + adr_l flag_ptr, idmap_kpti_bbml3_flag __idmap_cpu_set_reserved_ttbr1 x16, x17 scondary_cpu_wait: diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 3fcac789b0a4..0b94837ac238 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -14,6 +14,7 @@ HAS_ADDRESS_AUTH_ARCH_QARMA5 HAS_ADDRESS_AUTH_IMP_DEF HAS_AMU_EXTN HAS_ARMv8_4_TTL +HAS_BBML3 HAS_CACHE_DIC HAS_CACHE_IDC HAS_CNP @@ -51,7 +52,6 @@ HAS_LS64_V HAS_LSUI HAS_MOPS HAS_NESTED_VIRT -HAS_BBML2_NOABORT HAS_PAN HAS_PMUV3 HAS_S1PIE From 879aca5119cd7487bac64089127927aaae233a63 Mon Sep 17 00:00:00 2001 From: Linu Cherian Date: Thu, 23 Jul 2026 10:10:33 +0530 Subject: [PATCH 12/14] arm64: cpufeature: Detect BBML3 based on ID_AA64MMFR2_EL1.BBM Add ID_AA64MMFR2_EL1.BBM based BBML3 feature detection in cpu_supports_bbml3() so that cpus with the feature would not have to be added into MIDR based supports_bbml3_list. Reviewed-by: Gavin Shan Reviewed-by: Anshuman Khandual Signed-off-by: Linu Cherian [will: Tidy up cpu_supports_bbml3()] Signed-off-by: Will Deacon --- arch/arm64/kernel/cpufeature.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 896bafdb00b1..4025d51d2d93 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2153,16 +2153,12 @@ bool cpu_supports_bbml3(void) MIDR_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf, 0xf), {} }; + u64 mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1); - if (!is_midr_in_range_list(supports_bbml3_list)) - return false; + if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) >= ID_AA64MMFR2_EL1_BBM_3) + return true; - /* - * We currently ignore the ID_AA64MMFR2_EL1 register, and only care - * about whether the MIDR check passes. - */ - - return true; + return is_midr_in_range_list(supports_bbml3_list); } static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope) From d8fc0793cf6862813d9bde224230e0edeafab88c Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Thu, 6 Aug 2026 16:31:28 +0000 Subject: [PATCH 13/14] iommu/arm-smmu-v3-sva: Use system_supports_bbml3() to detect CPU feature Commit 94104e3cfa80 ("arm64: cpufeature: Rename BBML2_NOABORT as BBML3") renamed the cpu_supports_bbml2_noabort() helper to cpu_supports_bbml3(), as the Linux-defined "noabort" semantics have now been incorporated into the architecture under the BBML3 feature. Update the caller in the SMMUv3 SVA driver to use the new function. There is a slightly oddity in that the SMMUv3 architecture already defined BBML2 in such a way that aborts were prohibited, so we use the BBML3 feature on the CPU to enable BBML2 in the SMMU. Fixes: 94104e3cfa80 ("arm64: cpufeature: Rename BBML2_NOABORT as BBML3") Signed-off-by: Will Deacon --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 1ed8a6f29dc4..01492fb52659 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -208,7 +208,7 @@ bool arm_smmu_sva_supported(struct arm_smmu_device *smmu) feat_mask |= ARM_SMMU_FEAT_VAX; } - if (system_supports_bbml2_noabort()) + if (system_supports_bbml3()) feat_mask |= ARM_SMMU_FEAT_BBML2; if ((smmu->features & feat_mask) != feat_mask) From d3359af21fc9e7a47577ff90e821b6510ec34dee Mon Sep 17 00:00:00 2001 From: Josh Poimboeuf Date: Tue, 11 Aug 2026 14:11:44 +0000 Subject: [PATCH 14/14] arm64: bti: Disable in-kernel BTI with recent versions of Clang The following BTI exception was seen when loading a livepatch module: Internal error: Oops - BTI: 0000000036000001 [#1] SMP pstate: 634004c9 (nZCv daIF +PAN -UAO +TCO +DIT -SSBS BTYPE=jc) pc : kill_orphaned_pgrp+0x0/0x150 lr : do_exit+0x498/0xaf0 [livepatch_combined] The problem is that the patch module's do_exit() is branching to a static function in vmlinux using a module PLT veneer (indirect branch), but the target function doesn't have a BTI landing pad. Clang 21+ omits the landing pad for static functions which can only be reached by a direct branch. That's normally fine for ordinary modules which only branch to global exported functions, but Mark Brown points out [1] that this isn't guaranteed if the module branches between sections. Futhermore, livepatch modules use klp relocations to reference arbitrary kernel symbols, so with CONFIG_RANDOMIZE_MODULE_REGION_FULL the module is far enough from the kernel that every R_AARCH64_CALL26 needs a PLT. Put Clang 21+ in the naughty corner alongside GCC, which suffers from the same issue, by disabling CONFIG_ARM64_BTI_KERNEL until we have a version of the toolchain with the problem resolved. Cc: Ard Biesheuvel Link: https://lore.kernel.org/r/da06bbd3-d04b-4d0f-b331-f5b91bc373a5@sirena.org.uk [1] Fixes: fd1e0fd71f65 ("arm64: Implement HAVE_LIVEPATCH") Signed-off-by: Josh Poimboeuf [will: Stitched together commit message, diff and bug number] Signed-off-by: Will Deacon --- arch/arm64/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b3afe0688919..fc57d90d92c1 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -2116,6 +2116,8 @@ config ARM64_BTI_KERNEL depends on !CC_IS_GCC || GCC_VERSION >= 100100 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 depends on !CC_IS_GCC + # https://github.com/llvm/llvm-project/issues/215547 + depends on !CC_IS_CLANG || CLANG_VERSION < 210000 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) help Build the kernel with Branch Target Identification annotations