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drm/i915/cx0: Read out power-down state of both TXs in PHY lane 0

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If the number of used lanes is 1 or 2 then the power-down state of both
TX lanes in PHY lane 0 should be read out. If 1 lane is used only 1 TX
lane will be checked, make sure both TXs are checked in this case.

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Fixes: 230d4c7481 ("drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state")
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251120172358.1282765-4-imre.deak@intel.com
This commit is contained in:
Imre Deak 2025-11-20 19:23:57 +02:00
parent 07ba4ecfd1
commit dc5b3ef88b
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/display/intel_cx0_phy.c
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@ -2209,7 +2209,7 @@ static int readout_enabled_lane_count(struct intel_encoder *encoder)
*/
max_tx_lane_count = DDI_PORT_WIDTH_GET(intel_de_read(display, DDI_BUF_CTL(encoder->port)));
if (!drm_WARN_ON(display->drm, max_tx_lane_count == 0))
max_tx_lane_count = roundup_pow_of_two(max_tx_lane_count);
max_tx_lane_count = round_up(max_tx_lane_count, 2);
for (tx_lane = 0; tx_lane < max_tx_lane_count; tx_lane++) {
u8 phy_lane_mask = tx_lane < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;