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drm/i915/ltphy: Add LT Phy Programming recipe tables

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Add the LT Phy programming recipe tables for eDP, DP & HDMI and a
function to use the correct table.

Bspec: 74667
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-9-suraj.kandpal@intel.com
This commit is contained in:
Suraj Kandpal 2025-11-01 08:54:56 +05:30
parent e1455196ad
commit dc5742b619
4 changed files with 1036 additions and 1 deletions
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29
drivers/gpu/drm/i915/display/intel_dpll.c
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@ -17,6 +17,7 @@
#include "intel_display_types.h"
#include "intel_dpio_phy.h"
#include "intel_dpll.h"
#include "intel_lt_phy.h"
#include "intel_lvds.h"
#include "intel_lvds_regs.h"
#include "intel_panel.h"
@ -1232,6 +1233,26 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder =
intel_get_crtc_new_encoder(state, crtc_state);
int ret;
ret = intel_lt_phy_pll_calc_state(crtc_state, encoder);
if (ret)
return ret;
/* TODO: Do the readback via intel_compute_shared_dplls() */
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
return 0;
}
static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
@ -1691,6 +1712,10 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
static const struct intel_dpll_global_funcs xe3plpd_dpll_funcs = {
.crtc_compute_clock = xe3plpd_crtc_compute_clock,
};
static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
.crtc_compute_clock = mtl_crtc_compute_clock,
};
@ -1789,7 +1814,9 @@ int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state,
void
intel_dpll_init_clock_hook(struct intel_display *display)
{
if (DISPLAY_VER(display) >= 14)
if (HAS_LT_PHY(display))
display->funcs.dpll = &xe3plpd_dpll_funcs;
else if (DISPLAY_VER(display) >= 14)
display->funcs.dpll = &mtl_dpll_funcs;
else if (display->platform.dg2)
display->funcs.dpll = &dg2_dpll_funcs;

11
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
View File

@ -267,6 +267,16 @@ struct intel_cx0pll_state {
bool tbt_mode;
};
struct intel_lt_phy_pll_state {
u32 clock; /* in kHz */
u8 addr_msb[13];
u8 addr_lsb[13];
u8 data[13][4];
u8 config[3];
bool ssc_enabled;
bool tbt_mode;
};
struct intel_dpll_hw_state {
union {
struct i9xx_dpll_hw_state i9xx;
@ -276,6 +286,7 @@ struct intel_dpll_hw_state {
struct icl_dpll_hw_state icl;
struct intel_mpllb_state mpllb;
struct intel_cx0pll_state cx0pll;
struct intel_lt_phy_pll_state ltpll;
};
};

992
drivers/gpu/drm/i915/display/intel_lt_phy.c
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File diff suppressed because it is too large Load Diff

5
drivers/gpu/drm/i915/display/intel_lt_phy.h
View File

@ -13,5 +13,10 @@ struct intel_crtc_state;
void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
int
intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder);
#define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
#endif /* __INTEL_LT_PHY_H__ */