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drm/amd/display: Enable RCO for HDMISTREAMCLK in DCN35

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[Why & How]
Enable root clock optimization for HDMISTREAMCLK and only
disable it when it's actively being used.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Daniel Miess 2024-03-15 15:26:33 -04:00 committed by Alex Deucher
parent beb9764aad
commit dbfb51d1d4
2 changed files with 13 additions and 2 deletions
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1
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -696,6 +696,7 @@ enum pg_hw_pipe_resources {
PG_OPP,
PG_OPTC,
PG_DPSTREAM,
PG_HDMISTREAM,
PG_HW_PIPE_RESOURCES_NUM_ELEMENT
};

14
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
View File

@ -988,6 +988,9 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
if (!hpo_frl_stream_enc_acquired && !hpo_dp_stream_enc_acquired)
update_state->pg_res_update[PG_HPO] = true;
if (hpo_frl_stream_enc_acquired)
update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true;
update_state->pg_res_update[PG_DWB] = true;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
@ -1125,6 +1128,9 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
if (hpo_frl_stream_enc_acquired || hpo_dp_stream_enc_acquired)
update_state->pg_res_update[PG_HPO] = true;
if (hpo_frl_stream_enc_acquired)
update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true;
}
/**
@ -1249,7 +1255,7 @@ void dcn35_root_clock_control(struct dc *dc,
if (!pg_cntl)
return;
/*enable root clock first when power up*/
if (power_on)
if (power_on) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
update_state->pg_pipe_res_update[PG_DPP][i]) {
@ -1260,6 +1266,8 @@ void dcn35_root_clock_control(struct dc *dc,
if (dc->hwseq->funcs.dpstream_root_clock_control)
dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);
}
}
for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
if (update_state->pg_pipe_res_update[PG_DSC][i]) {
if (power_on) {
@ -1272,7 +1280,7 @@ void dcn35_root_clock_control(struct dc *dc,
}
}
/*disable root clock first when power down*/
if (!power_on)
if (!power_on) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
update_state->pg_pipe_res_update[PG_DPP][i]) {
@ -1283,6 +1291,8 @@ void dcn35_root_clock_control(struct dc *dc,
if (dc->hwseq->funcs.dpstream_root_clock_control)
dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);
}
}
}
void dcn35_prepare_bandwidth(