From 507c93a22c84209469fb03238ccdc5da3c6417fc Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Mon, 8 Oct 2018 11:23:47 -0500 Subject: [PATCH 1/3] clk: renesas: r7s9210: Add SDHI clocks Add SDHI clocks for RZ/A2 Signed-off-by: Chris Brandt Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r7s9210-cpg-mssr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c index 5135f13ec628..9056da15dc72 100644 --- a/drivers/clk/renesas/r7s9210-cpg-mssr.c +++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c @@ -98,6 +98,11 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = { DEF_MOD_STB("spi2", 95, R7S9210_CLK_P1), DEF_MOD_STB("spi1", 96, R7S9210_CLK_P1), DEF_MOD_STB("spi0", 97, R7S9210_CLK_P1), + + DEF_MOD_STB("sdhi11", 100, R7S9210_CLK_B), + DEF_MOD_STB("sdhi10", 101, R7S9210_CLK_B), + DEF_MOD_STB("sdhi01", 102, R7S9210_CLK_B), + DEF_MOD_STB("sdhi00", 103, R7S9210_CLK_B), }; /* The clock dividers in the table vary based on DT and register settings */ From 6f44610c30c5f10a8ea06bd714015cc4d2e534f5 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 2 Nov 2018 22:25:54 +0300 Subject: [PATCH 2/3] clk: renesas: r8a77970: Add RPC clocks On R-Car V3M (R8A77970), the RPC/RPCD2 clocks are output by the common divider. Describe them, as well as the RPC-IF module clock. Signed-off-by: Sergei Shtylyov Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a77970-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c index 2015e45543e9..9d845ebd7355 100644 --- a/drivers/clk/renesas/r8a77970-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c @@ -91,6 +91,9 @@ static const struct cpg_core_clk r8a77970_core_clks[] __initconst = { CLK_PLL1_DIV2), DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2), + DEF_FIXED("rpc", R8A77970_CLK_RPC, CLK_PLL1_DIV2, 5, 1), + DEF_FIXED("rpcd2", R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1), + DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1), @@ -152,6 +155,7 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = { DEF_MOD("gpio1", 911, R8A77970_CLK_CP), DEF_MOD("gpio0", 912, R8A77970_CLK_CP), DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2), + DEF_MOD("rpc-if", 917, R8A77970_CLK_RPC), DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2), DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2), DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2), From eb38c119dd91c61de26f67050671a84064554f7d Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Wed, 7 Nov 2018 12:35:56 -0500 Subject: [PATCH 3/3] clk: renesas: r7s9210: Add USB clocks Add USB clocks for RZ/A2 Signed-off-by: Chris Brandt Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r7s9210-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c index 9056da15dc72..e0793a9eb668 100644 --- a/drivers/clk/renesas/r7s9210-cpg-mssr.c +++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c @@ -87,6 +87,8 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = { DEF_MOD_STB("scif1", 46, R7S9210_CLK_P1C), DEF_MOD_STB("scif0", 47, R7S9210_CLK_P1C), + DEF_MOD_STB("usb1", 60, R7S9210_CLK_B), + DEF_MOD_STB("usb0", 61, R7S9210_CLK_B), DEF_MOD_STB("ether1", 64, R7S9210_CLK_B), DEF_MOD_STB("ether0", 65, R7S9210_CLK_B),