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LoongArch: Handle new atomic instructions for probes

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The atomic instructions sc.q, llacq.{w/d}, screl.{w/d} were newly added
in the LoongArch Reference Manual v1.10, it is necessary to handle them
in insns_not_supported() to avoid putting a breakpoint in the middle of
a ll/sc atomic sequence, otherwise it will loop forever for kprobes and
uprobes.

Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This commit is contained in:
Tiezhu Yang 2025-10-02 22:39:35 +08:00 committed by Huacai Chen
parent 892979b0a9
commit db740f5689
2 changed files with 17 additions and 0 deletions
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5
arch/loongarch/include/asm/inst.h
View File

@ -77,6 +77,10 @@ enum reg2_op {
iocsrwrh_op = 0x19205,
iocsrwrw_op = 0x19206,
iocsrwrd_op = 0x19207,
llacqw_op = 0xe15e0,
screlw_op = 0xe15e1,
llacqd_op = 0xe15e2,
screld_op = 0xe15e3,
};
enum reg2i5_op {
@ -189,6 +193,7 @@ enum reg3_op {
fldxd_op = 0x7068,
fstxs_op = 0x7070,
fstxd_op = 0x7078,
scq_op = 0x70ae,
amswapw_op = 0x70c0,
amswapd_op = 0x70c1,
amaddw_op = 0x70c2,

12
arch/loongarch/kernel/inst.c
View File

@ -141,6 +141,9 @@ bool insns_not_supported(union loongarch_instruction insn)
case amswapw_op ... ammindbdu_op:
pr_notice("atomic memory access instructions are not supported\n");
return true;
case scq_op:
pr_notice("sc.q instruction is not supported\n");
return true;
}
switch (insn.reg2i14_format.opcode) {
@ -152,6 +155,15 @@ bool insns_not_supported(union loongarch_instruction insn)
return true;
}
switch (insn.reg2_format.opcode) {
case llacqw_op:
case llacqd_op:
case screlw_op:
case screld_op:
pr_notice("llacq and screl instructions are not supported\n");
return true;
}
switch (insn.reg1i21_format.opcode) {
case bceqz_op:
pr_notice("bceqz and bcnez instructions are not supported\n");