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drm/tegra: dp: Read TPS3 capability from sink
The TPS3 capability can be exposed by DP 1.2 and later sinks if they support the alternative training pattern for channel equalization. Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -11,6 +11,7 @@
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static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps)
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{
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caps->enhanced_framing = false;
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caps->tps3_supported = false;
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caps->fast_training = false;
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}
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@ -18,6 +19,7 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
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const struct drm_dp_link_caps *src)
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{
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dest->enhanced_framing = src->enhanced_framing;
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dest->tps3_supported = src->tps3_supported;
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dest->fast_training = src->fast_training;
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}
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@ -63,6 +65,7 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
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link->max_lanes = drm_dp_max_lane_count(dpcd);
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link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd);
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link->caps.tps3_supported = drm_dp_tps3_supported(dpcd);
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link->caps.fast_training = drm_dp_fast_training_cap(dpcd);
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link->rate = link->max_rate;
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@ -22,6 +22,13 @@ struct drm_dp_link_caps {
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*/
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bool enhanced_framing;
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/**
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* tps3_supported:
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*
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* training pattern sequence 3 supported for equalization
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*/
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bool tps3_supported;
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/**
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* @fast_training:
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*
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