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hinic3: Command Queue framework
Add Command Queue framework initialization. It is used to set the related table items of the driver and obtain the HW configuration. Co-developed-by: Xin Guo <guoxin09@huawei.com> Signed-off-by: Xin Guo <guoxin09@huawei.com> Co-developed-by: Zhu Yikai <zhuyikai1@h-partners.com> Signed-off-by: Zhu Yikai <zhuyikai1@h-partners.com> Signed-off-by: Fan Gong <gongfan1@huawei.com> Link: https://patch.msgid.link/1aeed56de39078bde8fff4597d7aa22d350058fc.1755673097.git.zhuyikai1@h-partners.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Fan Gong
Jakub Kicinski
parent
c4bbfd9b0d
commit
db03a1ced6
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@ -3,7 +3,8 @@
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obj-$(CONFIG_HINIC3) += hinic3.o
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hinic3-objs := hinic3_common.o \
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hinic3-objs := hinic3_cmdq.o \
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hinic3_common.o \
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hinic3_eqs.o \
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hinic3_hw_cfg.o \
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hinic3_hw_comm.o \
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407
drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c
Normal file
407
drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c
Normal file
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@ -0,0 +1,407 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved.
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#include <linux/bitfield.h>
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#include <linux/dma-mapping.h>
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#include "hinic3_cmdq.h"
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#include "hinic3_hwdev.h"
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#include "hinic3_hwif.h"
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#include "hinic3_mbox.h"
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#define CMDQ_BUF_SIZE 2048
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#define CMDQ_WQEBB_SIZE 64
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#define CMDQ_CTXT_CURR_WQE_PAGE_PFN_MASK GENMASK_ULL(51, 0)
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#define CMDQ_CTXT_EQ_ID_MASK GENMASK_ULL(60, 53)
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#define CMDQ_CTXT_CEQ_ARM_MASK BIT_ULL(61)
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#define CMDQ_CTXT_CEQ_EN_MASK BIT_ULL(62)
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#define CMDQ_CTXT_HW_BUSY_BIT_MASK BIT_ULL(63)
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#define CMDQ_CTXT_WQ_BLOCK_PFN_MASK GENMASK_ULL(51, 0)
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#define CMDQ_CTXT_CI_MASK GENMASK_ULL(63, 52)
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#define CMDQ_CTXT_SET(val, member) \
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FIELD_PREP(CMDQ_CTXT_##member##_MASK, val)
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#define CMDQ_PFN(addr) ((addr) >> 12)
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/* cmdq work queue's chip logical address table is up to 512B */
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#define CMDQ_WQ_CLA_SIZE 512
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/* Completion codes: send, direct sync, force stop */
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#define CMDQ_SEND_CMPT_CODE 10
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#define CMDQ_DIRECT_SYNC_CMPT_CODE 11
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#define CMDQ_FORCE_STOP_CMPT_CODE 12
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#define CMDQ_WQE_NUM_WQEBBS 1
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static struct cmdq_wqe *cmdq_read_wqe(struct hinic3_wq *wq, u16 *ci)
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{
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if (hinic3_wq_get_used(wq) == 0)
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return NULL;
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*ci = wq->cons_idx & wq->idx_mask;
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return get_q_element(&wq->qpages, wq->cons_idx, NULL);
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}
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void hinic3_free_cmd_buf(struct hinic3_hwdev *hwdev,
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struct hinic3_cmd_buf *cmd_buf)
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{
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struct hinic3_cmdqs *cmdqs;
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if (!refcount_dec_and_test(&cmd_buf->ref_cnt))
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return;
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cmdqs = hwdev->cmdqs;
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dma_pool_free(cmdqs->cmd_buf_pool, cmd_buf->buf, cmd_buf->dma_addr);
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kfree(cmd_buf);
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}
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static void cmdq_clear_cmd_buf(struct hinic3_cmdq_cmd_info *cmd_info,
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struct hinic3_hwdev *hwdev)
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{
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if (cmd_info->buf_in) {
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hinic3_free_cmd_buf(hwdev, cmd_info->buf_in);
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cmd_info->buf_in = NULL;
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}
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}
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static void cmdq_init_queue_ctxt(struct hinic3_hwdev *hwdev, u8 cmdq_id,
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struct comm_cmdq_ctxt_info *ctxt_info)
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{
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const struct hinic3_cmdqs *cmdqs;
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u64 cmdq_first_block_paddr, pfn;
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const struct hinic3_wq *wq;
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cmdqs = hwdev->cmdqs;
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wq = &cmdqs->cmdq[cmdq_id].wq;
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pfn = CMDQ_PFN(hinic3_wq_get_first_wqe_page_addr(wq));
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ctxt_info->curr_wqe_page_pfn =
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cpu_to_le64(CMDQ_CTXT_SET(1, HW_BUSY_BIT) |
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CMDQ_CTXT_SET(1, CEQ_EN) |
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CMDQ_CTXT_SET(1, CEQ_ARM) |
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CMDQ_CTXT_SET(0, EQ_ID) |
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CMDQ_CTXT_SET(pfn, CURR_WQE_PAGE_PFN));
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if (!hinic3_wq_is_0_level_cla(wq)) {
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cmdq_first_block_paddr = cmdqs->wq_block_paddr;
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pfn = CMDQ_PFN(cmdq_first_block_paddr);
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}
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ctxt_info->wq_block_pfn = cpu_to_le64(CMDQ_CTXT_SET(wq->cons_idx, CI) |
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CMDQ_CTXT_SET(pfn, WQ_BLOCK_PFN));
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}
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static int init_cmdq(struct hinic3_cmdq *cmdq, struct hinic3_hwdev *hwdev,
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enum hinic3_cmdq_type q_type)
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{
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int err;
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cmdq->cmdq_type = q_type;
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cmdq->wrapped = 1;
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cmdq->hwdev = hwdev;
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spin_lock_init(&cmdq->cmdq_lock);
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cmdq->cmd_infos = kcalloc(cmdq->wq.q_depth, sizeof(*cmdq->cmd_infos),
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GFP_KERNEL);
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if (!cmdq->cmd_infos) {
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err = -ENOMEM;
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return err;
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}
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return 0;
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}
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static int hinic3_set_cmdq_ctxt(struct hinic3_hwdev *hwdev, u8 cmdq_id)
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{
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struct comm_cmd_set_cmdq_ctxt cmdq_ctxt = {};
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struct mgmt_msg_params msg_params = {};
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int err;
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cmdq_init_queue_ctxt(hwdev, cmdq_id, &cmdq_ctxt.ctxt);
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cmdq_ctxt.func_id = hinic3_global_func_id(hwdev);
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cmdq_ctxt.cmdq_id = cmdq_id;
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mgmt_msg_params_init_default(&msg_params, &cmdq_ctxt,
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sizeof(cmdq_ctxt));
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err = hinic3_send_mbox_to_mgmt(hwdev, MGMT_MOD_COMM,
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COMM_CMD_SET_CMDQ_CTXT, &msg_params);
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if (err || cmdq_ctxt.head.status) {
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dev_err(hwdev->dev, "Failed to set cmdq ctxt, err: %d, status: 0x%x\n",
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err, cmdq_ctxt.head.status);
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return -EFAULT;
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}
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return 0;
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}
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static int hinic3_set_cmdq_ctxts(struct hinic3_hwdev *hwdev)
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{
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struct hinic3_cmdqs *cmdqs = hwdev->cmdqs;
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u8 cmdq_type;
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int err;
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for (cmdq_type = 0; cmdq_type < cmdqs->cmdq_num; cmdq_type++) {
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err = hinic3_set_cmdq_ctxt(hwdev, cmdq_type);
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if (err)
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return err;
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}
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cmdqs->status |= HINIC3_CMDQ_ENABLE;
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cmdqs->disable_flag = 0;
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return 0;
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}
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static int create_cmdq_wq(struct hinic3_hwdev *hwdev,
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struct hinic3_cmdqs *cmdqs)
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{
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u8 cmdq_type;
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int err;
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for (cmdq_type = 0; cmdq_type < cmdqs->cmdq_num; cmdq_type++) {
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err = hinic3_wq_create(hwdev, &cmdqs->cmdq[cmdq_type].wq,
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CMDQ_DEPTH, CMDQ_WQEBB_SIZE);
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if (err) {
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dev_err(hwdev->dev, "Failed to create cmdq wq\n");
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goto err_destroy_wq;
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}
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}
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/* 1-level Chip Logical Address (CLA) must put all
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* cmdq's wq page addr in one wq block
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*/
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if (!hinic3_wq_is_0_level_cla(&cmdqs->cmdq[HINIC3_CMDQ_SYNC].wq)) {
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if (cmdqs->cmdq[HINIC3_CMDQ_SYNC].wq.qpages.num_pages >
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CMDQ_WQ_CLA_SIZE / sizeof(u64)) {
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err = -EINVAL;
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dev_err(hwdev->dev,
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"Cmdq number of wq pages exceeds limit: %lu\n",
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CMDQ_WQ_CLA_SIZE / sizeof(u64));
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goto err_destroy_wq;
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}
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cmdqs->wq_block_vaddr =
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dma_alloc_coherent(hwdev->dev, HINIC3_MIN_PAGE_SIZE,
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&cmdqs->wq_block_paddr, GFP_KERNEL);
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if (!cmdqs->wq_block_vaddr) {
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err = -ENOMEM;
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goto err_destroy_wq;
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}
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for (cmdq_type = 0; cmdq_type < cmdqs->cmdq_num; cmdq_type++)
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memcpy((u8 *)cmdqs->wq_block_vaddr +
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CMDQ_WQ_CLA_SIZE * cmdq_type,
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cmdqs->cmdq[cmdq_type].wq.wq_block_vaddr,
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cmdqs->cmdq[cmdq_type].wq.qpages.num_pages *
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sizeof(__be64));
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}
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return 0;
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err_destroy_wq:
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while (cmdq_type > 0) {
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cmdq_type--;
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hinic3_wq_destroy(hwdev, &cmdqs->cmdq[cmdq_type].wq);
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}
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return err;
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}
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static void destroy_cmdq_wq(struct hinic3_hwdev *hwdev,
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struct hinic3_cmdqs *cmdqs)
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{
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u8 cmdq_type;
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if (cmdqs->wq_block_vaddr)
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dma_free_coherent(hwdev->dev, HINIC3_MIN_PAGE_SIZE,
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cmdqs->wq_block_vaddr, cmdqs->wq_block_paddr);
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for (cmdq_type = 0; cmdq_type < cmdqs->cmdq_num; cmdq_type++)
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hinic3_wq_destroy(hwdev, &cmdqs->cmdq[cmdq_type].wq);
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}
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static int init_cmdqs(struct hinic3_hwdev *hwdev)
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{
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struct hinic3_cmdqs *cmdqs;
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cmdqs = kzalloc(sizeof(*cmdqs), GFP_KERNEL);
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if (!cmdqs)
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return -ENOMEM;
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hwdev->cmdqs = cmdqs;
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cmdqs->hwdev = hwdev;
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cmdqs->cmdq_num = hwdev->max_cmdq;
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cmdqs->cmd_buf_pool = dma_pool_create("hinic3_cmdq", hwdev->dev,
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CMDQ_BUF_SIZE, CMDQ_BUF_SIZE, 0);
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if (!cmdqs->cmd_buf_pool) {
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dev_err(hwdev->dev, "Failed to create cmdq buffer pool\n");
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kfree(cmdqs);
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return -ENOMEM;
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}
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return 0;
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}
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static void cmdq_flush_sync_cmd(struct hinic3_cmdq_cmd_info *cmd_info)
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{
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if (cmd_info->cmd_type != HINIC3_CMD_TYPE_DIRECT_RESP)
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return;
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cmd_info->cmd_type = HINIC3_CMD_TYPE_FORCE_STOP;
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if (cmd_info->cmpt_code &&
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*cmd_info->cmpt_code == CMDQ_SEND_CMPT_CODE)
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*cmd_info->cmpt_code = CMDQ_FORCE_STOP_CMPT_CODE;
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if (cmd_info->done) {
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complete(cmd_info->done);
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cmd_info->done = NULL;
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cmd_info->cmpt_code = NULL;
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cmd_info->direct_resp = NULL;
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cmd_info->errcode = NULL;
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}
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}
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static void hinic3_cmdq_flush_cmd(struct hinic3_cmdq *cmdq)
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{
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struct hinic3_cmdq_cmd_info *cmd_info;
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u16 ci;
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spin_lock_bh(&cmdq->cmdq_lock);
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while (cmdq_read_wqe(&cmdq->wq, &ci)) {
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hinic3_wq_put_wqebbs(&cmdq->wq, CMDQ_WQE_NUM_WQEBBS);
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cmd_info = &cmdq->cmd_infos[ci];
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if (cmd_info->cmd_type == HINIC3_CMD_TYPE_DIRECT_RESP)
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cmdq_flush_sync_cmd(cmd_info);
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}
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spin_unlock_bh(&cmdq->cmdq_lock);
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}
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void hinic3_cmdq_flush_sync_cmd(struct hinic3_hwdev *hwdev)
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{
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struct hinic3_cmdq *cmdq;
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u16 wqe_cnt, wqe_idx, i;
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struct hinic3_wq *wq;
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cmdq = &hwdev->cmdqs->cmdq[HINIC3_CMDQ_SYNC];
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spin_lock_bh(&cmdq->cmdq_lock);
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wq = &cmdq->wq;
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wqe_cnt = hinic3_wq_get_used(wq);
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for (i = 0; i < wqe_cnt; i++) {
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wqe_idx = (wq->cons_idx + i) & wq->idx_mask;
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cmdq_flush_sync_cmd(cmdq->cmd_infos + wqe_idx);
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}
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spin_unlock_bh(&cmdq->cmdq_lock);
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}
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static void hinic3_cmdq_reset_all_cmd_buf(struct hinic3_cmdq *cmdq)
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{
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u16 i;
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for (i = 0; i < cmdq->wq.q_depth; i++)
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cmdq_clear_cmd_buf(&cmdq->cmd_infos[i], cmdq->hwdev);
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}
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int hinic3_reinit_cmdq_ctxts(struct hinic3_hwdev *hwdev)
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{
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struct hinic3_cmdqs *cmdqs = hwdev->cmdqs;
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u8 cmdq_type;
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for (cmdq_type = 0; cmdq_type < cmdqs->cmdq_num; cmdq_type++) {
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hinic3_cmdq_flush_cmd(&cmdqs->cmdq[cmdq_type]);
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hinic3_cmdq_reset_all_cmd_buf(&cmdqs->cmdq[cmdq_type]);
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cmdqs->cmdq[cmdq_type].wrapped = 1;
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hinic3_wq_reset(&cmdqs->cmdq[cmdq_type].wq);
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}
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return hinic3_set_cmdq_ctxts(hwdev);
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}
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int hinic3_cmdqs_init(struct hinic3_hwdev *hwdev)
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{
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struct hinic3_cmdqs *cmdqs;
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void __iomem *db_base;
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u8 cmdq_type;
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int err;
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err = init_cmdqs(hwdev);
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if (err)
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goto err_out;
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cmdqs = hwdev->cmdqs;
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err = create_cmdq_wq(hwdev, cmdqs);
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if (err)
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goto err_free_cmdqs;
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err = hinic3_alloc_db_addr(hwdev, &db_base, NULL);
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if (err) {
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dev_err(hwdev->dev, "Failed to allocate doorbell address\n");
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goto err_destroy_cmdq_wq;
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}
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cmdqs->cmdqs_db_base = db_base;
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for (cmdq_type = 0; cmdq_type < cmdqs->cmdq_num; cmdq_type++) {
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err = init_cmdq(&cmdqs->cmdq[cmdq_type], hwdev, cmdq_type);
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if (err) {
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dev_err(hwdev->dev,
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"Failed to initialize cmdq type : %d\n",
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cmdq_type);
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goto err_free_cmd_infos;
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}
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}
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err = hinic3_set_cmdq_ctxts(hwdev);
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if (err)
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goto err_free_cmd_infos;
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return 0;
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err_free_cmd_infos:
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while (cmdq_type > 0) {
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cmdq_type--;
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kfree(cmdqs->cmdq[cmdq_type].cmd_infos);
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}
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hinic3_free_db_addr(hwdev, cmdqs->cmdqs_db_base);
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err_destroy_cmdq_wq:
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destroy_cmdq_wq(hwdev, cmdqs);
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err_free_cmdqs:
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dma_pool_destroy(cmdqs->cmd_buf_pool);
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kfree(cmdqs);
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err_out:
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return err;
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}
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void hinic3_cmdqs_free(struct hinic3_hwdev *hwdev)
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{
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struct hinic3_cmdqs *cmdqs = hwdev->cmdqs;
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u8 cmdq_type;
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cmdqs->status &= ~HINIC3_CMDQ_ENABLE;
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for (cmdq_type = 0; cmdq_type < cmdqs->cmdq_num; cmdq_type++) {
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hinic3_cmdq_flush_cmd(&cmdqs->cmdq[cmdq_type]);
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hinic3_cmdq_reset_all_cmd_buf(&cmdqs->cmdq[cmdq_type]);
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kfree(cmdqs->cmdq[cmdq_type].cmd_infos);
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}
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hinic3_free_db_addr(hwdev, cmdqs->cmdqs_db_base);
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destroy_cmdq_wq(hwdev, cmdqs);
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dma_pool_destroy(cmdqs->cmd_buf_pool);
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kfree(cmdqs);
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}
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bool hinic3_cmdq_idle(struct hinic3_cmdq *cmdq)
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{
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||||
return hinic3_wq_get_used(&cmdq->wq) == 0;
|
||||
}
|
||||
151
drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.h
Normal file
151
drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.h
Normal file
|
|
@ -0,0 +1,151 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
|
||||
|
||||
#ifndef _HINIC3_CMDQ_H_
|
||||
#define _HINIC3_CMDQ_H_
|
||||
|
||||
#include <linux/dmapool.h>
|
||||
|
||||
#include "hinic3_hw_intf.h"
|
||||
#include "hinic3_wq.h"
|
||||
|
||||
#define CMDQ_DEPTH 4096
|
||||
|
||||
struct cmdq_db {
|
||||
__le32 db_head;
|
||||
__le32 db_info;
|
||||
};
|
||||
|
||||
/* hw defined cmdq wqe header */
|
||||
struct cmdq_header {
|
||||
__le32 header_info;
|
||||
__le32 saved_data;
|
||||
};
|
||||
|
||||
struct cmdq_lcmd_bufdesc {
|
||||
struct hinic3_sge sge;
|
||||
__le64 rsvd2;
|
||||
__le64 rsvd3;
|
||||
};
|
||||
|
||||
struct cmdq_status {
|
||||
__le32 status_info;
|
||||
};
|
||||
|
||||
struct cmdq_ctrl {
|
||||
__le32 ctrl_info;
|
||||
};
|
||||
|
||||
struct cmdq_direct_resp {
|
||||
__le64 val;
|
||||
__le64 rsvd;
|
||||
};
|
||||
|
||||
struct cmdq_completion {
|
||||
union {
|
||||
struct hinic3_sge sge;
|
||||
struct cmdq_direct_resp direct;
|
||||
} resp;
|
||||
};
|
||||
|
||||
struct cmdq_wqe_scmd {
|
||||
struct cmdq_header header;
|
||||
__le64 rsvd3;
|
||||
struct cmdq_status status;
|
||||
struct cmdq_ctrl ctrl;
|
||||
struct cmdq_completion completion;
|
||||
__le32 rsvd10[6];
|
||||
};
|
||||
|
||||
struct cmdq_wqe_lcmd {
|
||||
struct cmdq_header header;
|
||||
struct cmdq_status status;
|
||||
struct cmdq_ctrl ctrl;
|
||||
struct cmdq_completion completion;
|
||||
struct cmdq_lcmd_bufdesc buf_desc;
|
||||
};
|
||||
|
||||
struct cmdq_wqe {
|
||||
union {
|
||||
struct cmdq_wqe_scmd wqe_scmd;
|
||||
struct cmdq_wqe_lcmd wqe_lcmd;
|
||||
};
|
||||
};
|
||||
|
||||
static_assert(sizeof(struct cmdq_wqe) == 64);
|
||||
|
||||
enum hinic3_cmdq_type {
|
||||
HINIC3_CMDQ_SYNC = 0,
|
||||
HINIC3_MAX_CMDQ_TYPES = 4
|
||||
};
|
||||
|
||||
enum hinic3_cmdq_status {
|
||||
HINIC3_CMDQ_ENABLE = BIT(0),
|
||||
};
|
||||
|
||||
enum hinic3_cmdq_cmd_type {
|
||||
HINIC3_CMD_TYPE_NONE,
|
||||
HINIC3_CMD_TYPE_DIRECT_RESP,
|
||||
HINIC3_CMD_TYPE_FAKE_TIMEOUT,
|
||||
HINIC3_CMD_TYPE_TIMEOUT,
|
||||
HINIC3_CMD_TYPE_FORCE_STOP,
|
||||
};
|
||||
|
||||
struct hinic3_cmd_buf {
|
||||
void *buf;
|
||||
dma_addr_t dma_addr;
|
||||
__le16 size;
|
||||
refcount_t ref_cnt;
|
||||
};
|
||||
|
||||
struct hinic3_cmdq_cmd_info {
|
||||
enum hinic3_cmdq_cmd_type cmd_type;
|
||||
struct completion *done;
|
||||
int *errcode;
|
||||
/* completion code */
|
||||
int *cmpt_code;
|
||||
__le64 *direct_resp;
|
||||
u64 cmdq_msg_id;
|
||||
struct hinic3_cmd_buf *buf_in;
|
||||
};
|
||||
|
||||
struct hinic3_cmdq {
|
||||
struct hinic3_wq wq;
|
||||
enum hinic3_cmdq_type cmdq_type;
|
||||
u8 wrapped;
|
||||
/* synchronize command submission with completions via event queue */
|
||||
spinlock_t cmdq_lock;
|
||||
struct hinic3_cmdq_cmd_info *cmd_infos;
|
||||
struct hinic3_hwdev *hwdev;
|
||||
};
|
||||
|
||||
struct hinic3_cmdqs {
|
||||
struct hinic3_hwdev *hwdev;
|
||||
struct hinic3_cmdq cmdq[HINIC3_MAX_CMDQ_TYPES];
|
||||
struct dma_pool *cmd_buf_pool;
|
||||
/* doorbell area */
|
||||
u8 __iomem *cmdqs_db_base;
|
||||
|
||||
/* When command queue uses multiple memory pages (1-level CLA), this
|
||||
* block will hold aggregated indirection table for all command queues
|
||||
* of cmdqs. Not used for small cmdq (0-level CLA).
|
||||
*/
|
||||
dma_addr_t wq_block_paddr;
|
||||
void *wq_block_vaddr;
|
||||
|
||||
u32 status;
|
||||
u32 disable_flag;
|
||||
u8 cmdq_num;
|
||||
};
|
||||
|
||||
int hinic3_cmdqs_init(struct hinic3_hwdev *hwdev);
|
||||
void hinic3_cmdqs_free(struct hinic3_hwdev *hwdev);
|
||||
|
||||
void hinic3_free_cmd_buf(struct hinic3_hwdev *hwdev,
|
||||
struct hinic3_cmd_buf *cmd_buf);
|
||||
|
||||
void hinic3_cmdq_flush_sync_cmd(struct hinic3_hwdev *hwdev);
|
||||
int hinic3_reinit_cmdq_ctxts(struct hinic3_hwdev *hwdev);
|
||||
bool hinic3_cmdq_idle(struct hinic3_cmdq *cmdq);
|
||||
|
||||
#endif
|
||||
|
|
@ -18,6 +18,13 @@ struct hinic3_dma_addr_align {
|
|||
dma_addr_t align_paddr;
|
||||
};
|
||||
|
||||
struct hinic3_sge {
|
||||
__le32 hi_addr;
|
||||
__le32 lo_addr;
|
||||
__le32 len;
|
||||
__le32 rsvd;
|
||||
};
|
||||
|
||||
int hinic3_dma_zalloc_coherent_align(struct device *dev, u32 size, u32 align,
|
||||
gfp_t flag,
|
||||
struct hinic3_dma_addr_align *mem_align);
|
||||
|
|
|
|||
|
|
@ -55,9 +55,9 @@ void hinic3_free_txqs(struct net_device *netdev)
|
|||
static void hinic3_set_buf_desc(struct hinic3_sq_bufdesc *buf_descs,
|
||||
dma_addr_t addr, u32 len)
|
||||
{
|
||||
buf_descs->hi_addr = upper_32_bits(addr);
|
||||
buf_descs->lo_addr = lower_32_bits(addr);
|
||||
buf_descs->len = len;
|
||||
buf_descs->hi_addr = cpu_to_le32(upper_32_bits(addr));
|
||||
buf_descs->lo_addr = cpu_to_le32(lower_32_bits(addr));
|
||||
buf_descs->len = cpu_to_le32(len);
|
||||
}
|
||||
|
||||
static int hinic3_tx_map_skb(struct net_device *netdev, struct sk_buff *skb,
|
||||
|
|
|
|||
|
|
@ -6,6 +6,110 @@
|
|||
#include "hinic3_hwdev.h"
|
||||
#include "hinic3_wq.h"
|
||||
|
||||
#define WQ_MIN_DEPTH 64
|
||||
#define WQ_MAX_DEPTH 65536
|
||||
#define WQ_PAGE_ADDR_SIZE sizeof(u64)
|
||||
#define WQ_MAX_NUM_PAGES (HINIC3_MIN_PAGE_SIZE / WQ_PAGE_ADDR_SIZE)
|
||||
|
||||
static int wq_init_wq_block(struct hinic3_hwdev *hwdev, struct hinic3_wq *wq)
|
||||
{
|
||||
struct hinic3_queue_pages *qpages = &wq->qpages;
|
||||
int i;
|
||||
|
||||
if (hinic3_wq_is_0_level_cla(wq)) {
|
||||
wq->wq_block_paddr = qpages->pages[0].align_paddr;
|
||||
wq->wq_block_vaddr = qpages->pages[0].align_vaddr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (wq->qpages.num_pages > WQ_MAX_NUM_PAGES) {
|
||||
dev_err(hwdev->dev, "wq num_pages exceed limit: %lu\n",
|
||||
WQ_MAX_NUM_PAGES);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
wq->wq_block_vaddr = dma_alloc_coherent(hwdev->dev,
|
||||
HINIC3_MIN_PAGE_SIZE,
|
||||
&wq->wq_block_paddr,
|
||||
GFP_KERNEL);
|
||||
if (!wq->wq_block_vaddr)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < qpages->num_pages; i++)
|
||||
wq->wq_block_vaddr[i] = cpu_to_be64(qpages->pages[i].align_paddr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wq_alloc_pages(struct hinic3_hwdev *hwdev, struct hinic3_wq *wq)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = hinic3_queue_pages_alloc(hwdev, &wq->qpages, 0);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = wq_init_wq_block(hwdev, wq);
|
||||
if (err) {
|
||||
hinic3_queue_pages_free(hwdev, &wq->qpages);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void wq_free_pages(struct hinic3_hwdev *hwdev, struct hinic3_wq *wq)
|
||||
{
|
||||
if (!hinic3_wq_is_0_level_cla(wq))
|
||||
dma_free_coherent(hwdev->dev,
|
||||
HINIC3_MIN_PAGE_SIZE,
|
||||
wq->wq_block_vaddr,
|
||||
wq->wq_block_paddr);
|
||||
|
||||
hinic3_queue_pages_free(hwdev, &wq->qpages);
|
||||
}
|
||||
|
||||
int hinic3_wq_create(struct hinic3_hwdev *hwdev, struct hinic3_wq *wq,
|
||||
u32 q_depth, u16 wqebb_size)
|
||||
{
|
||||
u32 wq_page_size;
|
||||
|
||||
if (q_depth < WQ_MIN_DEPTH || q_depth > WQ_MAX_DEPTH ||
|
||||
!is_power_of_2(q_depth) || !is_power_of_2(wqebb_size)) {
|
||||
dev_err(hwdev->dev, "Invalid WQ: q_depth %u, wqebb_size %u\n",
|
||||
q_depth, wqebb_size);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
wq_page_size = ALIGN(hwdev->wq_page_size, HINIC3_MIN_PAGE_SIZE);
|
||||
|
||||
memset(wq, 0, sizeof(*wq));
|
||||
wq->q_depth = q_depth;
|
||||
wq->idx_mask = q_depth - 1;
|
||||
|
||||
hinic3_queue_pages_init(&wq->qpages, q_depth, wq_page_size, wqebb_size);
|
||||
|
||||
return wq_alloc_pages(hwdev, wq);
|
||||
}
|
||||
|
||||
void hinic3_wq_destroy(struct hinic3_hwdev *hwdev, struct hinic3_wq *wq)
|
||||
{
|
||||
wq_free_pages(hwdev, wq);
|
||||
}
|
||||
|
||||
void hinic3_wq_reset(struct hinic3_wq *wq)
|
||||
{
|
||||
struct hinic3_queue_pages *qpages = &wq->qpages;
|
||||
u16 pg_idx;
|
||||
|
||||
wq->cons_idx = 0;
|
||||
wq->prod_idx = 0;
|
||||
|
||||
for (pg_idx = 0; pg_idx < qpages->num_pages; pg_idx++)
|
||||
memset(qpages->pages[pg_idx].align_vaddr, 0, qpages->page_size);
|
||||
}
|
||||
|
||||
void hinic3_wq_get_multi_wqebbs(struct hinic3_wq *wq,
|
||||
u16 num_wqebbs, u16 *prod_idx,
|
||||
struct hinic3_sq_bufdesc **first_part_wqebbs,
|
||||
|
|
@ -27,3 +131,8 @@ void hinic3_wq_get_multi_wqebbs(struct hinic3_wq *wq,
|
|||
*second_part_wqebbs = get_q_element(&wq->qpages, idx, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
bool hinic3_wq_is_0_level_cla(const struct hinic3_wq *wq)
|
||||
{
|
||||
return wq->qpages.num_pages == 1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -10,10 +10,10 @@
|
|||
|
||||
struct hinic3_sq_bufdesc {
|
||||
/* 31-bits Length, L2NIC only uses length[17:0] */
|
||||
u32 len;
|
||||
u32 rsvd;
|
||||
u32 hi_addr;
|
||||
u32 lo_addr;
|
||||
__le32 len;
|
||||
__le32 rsvd;
|
||||
__le32 hi_addr;
|
||||
__le32 lo_addr;
|
||||
};
|
||||
|
||||
/* Work queue is used to submit elements (tx, rx, cmd) to hw.
|
||||
|
|
@ -59,6 +59,7 @@ static inline void *hinic3_wq_get_one_wqebb(struct hinic3_wq *wq, u16 *pi)
|
|||
{
|
||||
*pi = wq->prod_idx & wq->idx_mask;
|
||||
wq->prod_idx++;
|
||||
|
||||
return get_q_element(&wq->qpages, *pi, NULL);
|
||||
}
|
||||
|
||||
|
|
@ -67,10 +68,20 @@ static inline void hinic3_wq_put_wqebbs(struct hinic3_wq *wq, u16 num_wqebbs)
|
|||
wq->cons_idx += num_wqebbs;
|
||||
}
|
||||
|
||||
static inline u64 hinic3_wq_get_first_wqe_page_addr(const struct hinic3_wq *wq)
|
||||
{
|
||||
return wq->qpages.pages[0].align_paddr;
|
||||
}
|
||||
|
||||
int hinic3_wq_create(struct hinic3_hwdev *hwdev, struct hinic3_wq *wq,
|
||||
u32 q_depth, u16 wqebb_size);
|
||||
void hinic3_wq_destroy(struct hinic3_hwdev *hwdev, struct hinic3_wq *wq);
|
||||
void hinic3_wq_reset(struct hinic3_wq *wq);
|
||||
void hinic3_wq_get_multi_wqebbs(struct hinic3_wq *wq,
|
||||
u16 num_wqebbs, u16 *prod_idx,
|
||||
struct hinic3_sq_bufdesc **first_part_wqebbs,
|
||||
struct hinic3_sq_bufdesc **second_part_wqebbs,
|
||||
u16 *first_part_wqebbs_num);
|
||||
bool hinic3_wq_is_0_level_cla(const struct hinic3_wq *wq);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user