mirror of
https://github.com/torvalds/linux.git
synced 2026-05-22 14:12:07 +02:00
Armv8 Juno/FVP/Vexpress updates for v7.1
1. The primary addition is initial support for Zena CSS that includes:
a new binding compatibility, a shared `zena-css.dtsi` description, and
an FVP device tree.
2. Extension of Corstone-1000 FVP platform support with binding updates
to add the new `arm,corstone1000-a320-fvp` platform, and the
`arm,corstone1000-ethos-u85` NPU integration.
Overall, this combines new platform enablement with some DTS layout
cleanup for Arm reference FVP based systems.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmnCQHUACgkQAEG6vDF+
4pgiqg//YYEnHS2nA3PgwsMwMYqKdUfLVZdE5wrwxbSck0zrDYynm8rsIdhkiLgJ
IY06ZUshziuyraXYlIssGJl3XfAb5mieUksXGaWmVRv3uTbWGZHmYyuKIGj3jDba
vkNi0d79ijoo8O5cDIJ8Uv/baVqOt26QxqIC1azI9yXkoYDXXL4Mv3olSS4M16/V
P/GVylL8FUWEGgDBVfm3lOHFIzHgibKfcmETRTRWWzzDMOSL0dYxRtrnb8uQc6A0
VpFkfHm2bZXaBbXDwmwV5vbv3nUwAq1J+AjyYOfCYNLCNm7cBKIgdJ1E/aH3UHQk
69BLGMdXgP5gXdtKLBXnOY0ZJmth2tRWOpKdUke5PDgkc3kA+Vw2vFRcFRMAKOZC
9Yt+0EsblJAqRH92T9AQ6QePoJx5bfHID1k3JTrCYLq5x/KeMY+3Q8HZund4mSA+
nrYDl5oYMKq2FJ9HTPpzBuiF8iFwe7jdtVkIl8X5jLyD1IM05SU2CoDEhvdM3bXp
ixejBshDLeg8iql6kSO6OpsEaFBW1GNk+rKMNyHzGiTLEtJQgaHF42yRRLJl7khG
XlK4fQH/NXjcLKGWtsJlA7YB1GOGAxgGRL2jnNhNXHUsXg9NYS2Ww93MUmRmV1D2
qPkJJ3oCdB5XHF5ZfahrAeOgwzbxlZjD3EZbJPohSOs/bgMUI7A=
=pqOI
-----END PGP SIGNATURE-----
Merge tag 'juno-updates-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
Armv8 Juno/FVP/Vexpress updates for v7.1
1. The primary addition is initial support for Zena CSS that includes:
a new binding compatibility, a shared `zena-css.dtsi` description, and
an FVP device tree.
2. Extension of Corstone-1000 FVP platform support with binding updates
to add the new `arm,corstone1000-a320-fvp` platform, and the
`arm,corstone1000-ethos-u85` NPU integration.
Overall, this combines new platform enablement with some DTS layout
cleanup for Arm reference FVP based systems.
* tag 'juno-updates-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: arm/corstone1000: Add corstone-1000-a320
arm64: dts: arm/corstone1000: Move FVP peripherals to separate .dtsi
arm64: dts: arm/corstone1000: Move cpu nodes
dt-bindings: npu: arm,ethos: Add "arm,corstone1000-ethos-u85"
dt-bindings: arm,corstone1000: Add "arm,corstone1000-a320-fvp"
arm64: dts: zena: Move SRAM into SoC and memory node out of SoC
arm64: dts: zena: Add support for Zena CSS
dt-bindings: arm: Add Zena CSS compatibility
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
commit
dadfceb3bc
|
|
@ -15,11 +15,11 @@ description: |+
|
|||
provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
|
||||
processors.
|
||||
|
||||
Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
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||||
systems for M-Class (or other) processors for adding sensors, connectivity,
|
||||
video, audio and machine learning at the edge System and security IPs to build
|
||||
a secure SoC for a range of rich IoT applications, for example gateways, smart
|
||||
cameras and embedded systems.
|
||||
Support for Cortex‑A32, Cortex‑A35, Cortex‑A53 and Cortex-A320 processors.
|
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Two expansion systems for M-Class (or other) processors for adding sensors,
|
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connectivity, video, audio and machine learning at the edge System and
|
||||
security IPs to build a secure SoC for a range of rich IoT applications, for
|
||||
example gateways, smart cameras and embedded systems.
|
||||
|
||||
Integrated Secure Enclave providing hardware Root of Trust and supporting
|
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seamless integration of the optional CryptoCell™-312 cryptographic
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|
|
@ -39,6 +39,11 @@ properties:
|
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implementation of this system. See ARM ecosystems FVP's.
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items:
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- const: arm,corstone1000-fvp
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- description: Corstone1000-A320 FVP is the Fixed Virtual Platform
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implementation of this system with Cortex-A320 cores and Ethos-U85
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NPU. See ARM ecosystems FVP's.
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items:
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- const: arm,corstone1000-a320-fvp
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additionalProperties: true
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|
|
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@ -119,6 +119,16 @@ properties:
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items:
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- const: arm,foundation-aarch64
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- const: arm,vexpress
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- description: Arm Zena Compute Subsystem Platforms
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Arm Zena Compute Subsystem (CSS) is a compute platform targeting
|
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the automotive sector. Arm Zena CSS is a high-performance Arm
|
||||
Cortex-A720AE Application Processor system augmented with an Arm
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||||
Cortex-R82AE based Safety Island and real-time domain.
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||||
items:
|
||||
- enum:
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- arm,zena-css-fvp
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- const: arm,zena-css
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- const: arm,vexpress
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arm,vexpress,position:
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description: When daughterboards are stacked on one site, their position
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|
|
|
|||
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|
@ -30,7 +30,7 @@ properties:
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|||
- fsl,imx93-npu
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- const: arm,ethos-u65
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||||
- items:
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||||
- {}
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- const: arm,corstone1000-ethos-u85
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- const: arm,ethos-u85
|
||||
|
||||
reg:
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||||
|
|
|
|||
|
|
@ -7,4 +7,6 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-a320-fvp.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += zena-css-fvp.dtb
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|
|
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15
arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts
Normal file
15
arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts
Normal file
|
|
@ -0,0 +1,15 @@
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|||
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (c) 2026, Arm Limited. All rights reserved.
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*
|
||||
*/
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/dts-v1/;
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#include "corstone1000-a320.dtsi"
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#include "corstone1000-fvp.dtsi"
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/ {
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model = "ARM Corstone1000-A320 FVP (Fixed Virtual Platform)";
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compatible = "arm,corstone1000-a320-fvp";
|
||||
};
|
||||
91
arch/arm64/boot/dts/arm/corstone1000-a320.dtsi
Normal file
91
arch/arm64/boot/dts/arm/corstone1000-a320.dtsi
Normal file
|
|
@ -0,0 +1,91 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright (c) 2026, Arm Limited. All rights reserved.
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||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
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|
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#include "corstone1000.dtsi"
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
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#size-cells = <1>;
|
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|
||||
cpus: cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu: cpu@0 {
|
||||
device_type = "cpu";
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||||
compatible = "arm,cortex-a320";
|
||||
reg = <0 0>;
|
||||
enable-method = "psci";
|
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next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
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cpu1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a320";
|
||||
reg = <0 0x100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a320";
|
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reg = <0 0x200>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a320";
|
||||
reg = <0 0x300>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
sram: sram@2400000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x02400000 0x200000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1c000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x1c000000 0x10000>,
|
||||
<0x1c040000 0x80000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
|
||||
soc {
|
||||
npu@1a050000 {
|
||||
compatible = "arm,corstone1000-ethos-u85", "arm,ethos-u85";
|
||||
reg = <0x1a050000 0x1400>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&refclk100mhz>, <&refclk100mhz>;
|
||||
clock-names = "core", "apb";
|
||||
sram = <&sram>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -8,70 +8,46 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "corstone1000.dtsi"
|
||||
#include "corstone1000-fvp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
|
||||
compatible = "arm,corstone1000-fvp";
|
||||
|
||||
smsc: ethernet@4010000 {
|
||||
compatible = "smsc,lan91c111";
|
||||
reg = <0x40100000 0x10000>;
|
||||
phy-mode = "mii";
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <2>;
|
||||
};
|
||||
cpus: cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vmmc_v3_3d: regulator-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmc_supply";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
cpu: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a35";
|
||||
reg = <0 0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
sdmmc0: mmc@40300000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x40300000 0x1000>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&vmmc_v3_3d>;
|
||||
clocks = <&smbclk>, <&refclk100mhz>;
|
||||
clock-names = "smclk", "apb_pclk";
|
||||
};
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a35";
|
||||
reg = <0 0x1>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
sdmmc1: mmc@50000000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x50000000 0x10000>;
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&vmmc_v3_3d>;
|
||||
clocks = <&smbclk>, <&refclk100mhz>;
|
||||
clock-names = "smclk", "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
&cpus {
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a35";
|
||||
reg = <0x1>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a35";
|
||||
reg = <0x2>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a35";
|
||||
reg = <0x3>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a35";
|
||||
reg = <0 0x2>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a35";
|
||||
reg = <0 0x3>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
44
arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi
Normal file
44
arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright (c) 2022, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2022, Linaro Limited. All rights reserved.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
smsc: ethernet@4010000 {
|
||||
compatible = "smsc,lan91c111";
|
||||
reg = <0x40100000 0x10000>;
|
||||
phy-mode = "mii";
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <2>;
|
||||
};
|
||||
|
||||
vmmc_v3_3d: regulator-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmc_supply";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sdmmc0: mmc@40300000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x40300000 0x1000>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&vmmc_v3_3d>;
|
||||
clocks = <&smbclk>, <&refclk100mhz>;
|
||||
clock-names = "smclk", "apb_pclk";
|
||||
};
|
||||
|
||||
sdmmc1: mmc@50000000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x50000000 0x10000>;
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&vmmc_v3_3d>;
|
||||
clocks = <&smbclk>, <&refclk100mhz>;
|
||||
clock-names = "smclk", "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
|
@ -13,6 +13,19 @@ / {
|
|||
model = "ARM Corstone1000 FPGA MPS3 board";
|
||||
compatible = "arm,corstone1000-mps3";
|
||||
|
||||
cpus: cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a35";
|
||||
reg = <0 0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
};
|
||||
|
||||
smsc: ethernet@4010000 {
|
||||
compatible = "smsc,lan9220", "smsc,lan9115";
|
||||
reg = <0x40100000 0x10000>;
|
||||
|
|
|
|||
|
|
@ -21,19 +21,6 @@ chosen {
|
|||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
cpus: cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a35";
|
||||
reg = <0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@88200000 {
|
||||
device_type = "memory";
|
||||
reg = <0x88200000 0x77e00000>;
|
||||
|
|
|
|||
63
arch/arm64/boot/dts/arm/zena-css-fvp.dts
Normal file
63
arch/arm64/boot/dts/arm/zena-css-fvp.dts
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) 2025, Arm Limited. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zena-css.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Zena CSS Fixed Virtual Platform";
|
||||
compatible = "arm,zena-css-fvp", "arm,zena-css", "arm,vexpress";
|
||||
|
||||
chosen {
|
||||
stdout-path = &soc_serial0;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
|
||||
/* ~2GB mapped at 2GB, another 2GB at 2TB */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x7f000000>,
|
||||
<0x00000200 0x00000000 0x00000000 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
virtio@30020000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x0 0x30020000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
virtio@30030000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x0 0x30030000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
virtio@30040000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x0 0x30040000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
virtio@30050000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x0 0x30050000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
virtio@30060000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x0 0x30060000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
virtio@30080000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x0 0x30080000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
769
arch/arm64/boot/dts/arm/zena-css.dtsi
Normal file
769
arch/arm64/boot/dts/arm/zena-css.dtsi
Normal file
|
|
@ -0,0 +1,769 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) 2025, Arm Limited. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
soc_clk24mhz: clock-24000000 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "refclk24mhz";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/*
|
||||
* The latency and residency numbers below are for illustrative
|
||||
* purposes only and may vary on actual silicon. These values are
|
||||
* considered just to demonstrate that the cpuidle governor logic
|
||||
* works.
|
||||
*/
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
cpu_sleep: cpu-sleep {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x10000>;
|
||||
entry-latency-us = <800>;
|
||||
exit-latency-us = <3200>;
|
||||
local-timer-stop;
|
||||
min-residency-us = <4200>;
|
||||
};
|
||||
|
||||
cluster_sleep: cluster-sleep {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <1000>;
|
||||
exit-latency-us = <3200>;
|
||||
local-timer-stop;
|
||||
min-residency-us = <4500>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 { cpu = <&cpu0>; };
|
||||
core1 { cpu = <&cpu1>; };
|
||||
core2 { cpu = <&cpu2>; };
|
||||
core3 { cpu = <&cpu3>; };
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 { cpu = <&cpu4>; };
|
||||
core1 { cpu = <&cpu5>; };
|
||||
core2 { cpu = <&cpu6>; };
|
||||
core3 { cpu = <&cpu7>; };
|
||||
};
|
||||
|
||||
cluster2 {
|
||||
core0 { cpu = <&cpu8>; };
|
||||
core1 { cpu = <&cpu9>; };
|
||||
core2 { cpu = <&cpu10>; };
|
||||
core3 { cpu = <&cpu11>; };
|
||||
};
|
||||
|
||||
cluster3 {
|
||||
core0 { cpu = <&cpu12>; };
|
||||
core1 { cpu = <&cpu13>; };
|
||||
core2 { cpu = <&cpu14>; };
|
||||
core3 { cpu = <&cpu15>; };
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x0000>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl0_l2_0>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl0_l2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl0_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu1: cpu@100 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x0100>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl0_l2_1>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl0_l2_1: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl0_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu2: cpu@200 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x0200>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl0_l2_2>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl0_l2_2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl0_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu3: cpu@300 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x0300>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl0_l2_3>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl0_l2_3: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl0_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu4: cpu@10000 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x10000>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl1_l2_0>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl1_l2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl1_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu5: cpu@10100 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x10100>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl1_l2_1>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl1_l2_1: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl1_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu6: cpu@10200 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x10200>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl1_l2_2>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl1_l2_2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl1_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu7: cpu@10300 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x10300>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl1_l2_3>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl1_l2_3: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl1_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu8: cpu@20000 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x20000>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl2_l2_0>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl2_l2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl2_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu9: cpu@20100 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x20100>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl2_l2_1>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl2_l2_1: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl2_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu10: cpu@20200 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x20200>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl2_l2_2>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl2_l2_2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl2_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu11: cpu@20300 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x20300>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl2_l2_3>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl2_l2_3: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl2_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu12: cpu@30000 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x30000>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl3_l2_0>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl3_l2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl3_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu13: cpu@30100 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x30100>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl3_l2_1>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl3_l2_1: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl3_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu14: cpu@30200 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x30200>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl3_l2_2>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl3_l2_2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl3_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu15: cpu@30300 {
|
||||
compatible = "arm,cortex-a720ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00 0x30300>;
|
||||
enable-method = "psci";
|
||||
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
cpu-idle-states = <&cpu_sleep &cluster_sleep>;
|
||||
next-level-cache = <&cl3_l2_3>;
|
||||
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
i-cache-size = <0x10000>;
|
||||
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <0x10000>;
|
||||
|
||||
cl3_l2_3: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x400>; /* 8-way set */
|
||||
cache-size = <0x80000>; /* 512KB */
|
||||
cache-unified;
|
||||
next-level-cache = <&cl3_l3>;
|
||||
};
|
||||
};
|
||||
|
||||
cl0_l3: l3-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x1000>; /* 16-way set */
|
||||
cache-size = <0x400000>; /* 4MB */
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
cl1_l3: l3-cache1 {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x1000>; /* 16-way set */
|
||||
cache-size = <0x400000>; /* 4MB */
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
cl2_l3: l3-cache2 {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x1000>; /* 16-way set */
|
||||
cache-size = <0x400000>; /* 4MB */
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
cl3_l3: l3-cache3 {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <0x1000>; /* 16-way set */
|
||||
cache-size = <0x400000>; /* 4MB */
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
scmi {
|
||||
compatible = "arm,scmi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mbox-names = "tx", "tx_reply", "rx";
|
||||
mboxes = <&mbox_db_tx 0 0 0>,
|
||||
<&mbox_db_rx 0 0 0>,
|
||||
<&mbox_db_rx 0 0 2>;
|
||||
shmem = <&scmi_shmem_tx &scmi_shmem_rx>;
|
||||
|
||||
scmi_dvfs: protocol@13 {
|
||||
reg = <0x13>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsu-pmu-0 {
|
||||
compatible = "arm,dsu-pmu";
|
||||
cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
dsu-pmu-1 {
|
||||
compatible = "arm,dsu-pmu";
|
||||
cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
dsu-pmu-2 {
|
||||
compatible = "arm,dsu-pmu";
|
||||
cpus = <&cpu8 &cpu9 &cpu10 &cpu11>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
dsu-pmu-3 {
|
||||
compatible = "arm,dsu-pmu";
|
||||
cpus = <&cpu12 &cpu13 &cpu14 &cpu15>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
sram: sram@104000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x0 0x00104000 0x0 0x00001000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x00104000 0x00001000>;
|
||||
|
||||
scmi_shmem_tx: scpshmem-sram-section@0 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x0 0x100>;
|
||||
};
|
||||
|
||||
scmi_shmem_rx: scpshmem-sram-section@100 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x100 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
timer@1a810000 {
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0x0 0x1a810000 0x0 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/*
|
||||
* Map child space [0x0..0x30000) to parent @ 0x1a810000
|
||||
*/
|
||||
ranges = <0x0 0x0 0x1a810000 0x00030000>;
|
||||
|
||||
frame@20000 {
|
||||
reg = <0x20000 0x10000>;
|
||||
frame-number = <0>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@20800000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
#redistributor-regions = <16>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ranges;
|
||||
|
||||
/*
|
||||
* With GIC-A720AE multiview enabled, GICR_TYPER.Last is
|
||||
* always reported as 1 on redistributor views other than
|
||||
* view 0. This breaks discovery of a single contiguous
|
||||
* GICR frame region, so each core is described with its own
|
||||
* redistributor region.
|
||||
*/
|
||||
reg = <0x0 0x20800000 0x0 0x10000>, /* GICD */
|
||||
<0x0 0x20880000 0x0 0x40000>, /* 16 * GICR */
|
||||
<0x0 0x208c0000 0x0 0x40000>,
|
||||
<0x0 0x20900000 0x0 0x40000>,
|
||||
<0x0 0x20940000 0x0 0x40000>,
|
||||
<0x0 0x20980000 0x0 0x40000>,
|
||||
<0x0 0x209c0000 0x0 0x40000>,
|
||||
<0x0 0x20a00000 0x0 0x40000>,
|
||||
<0x0 0x20a40000 0x0 0x40000>,
|
||||
<0x0 0x20a80000 0x0 0x40000>,
|
||||
<0x0 0x20ac0000 0x0 0x40000>,
|
||||
<0x0 0x20b00000 0x0 0x40000>,
|
||||
<0x0 0x20b40000 0x0 0x40000>,
|
||||
<0x0 0x20b80000 0x0 0x40000>,
|
||||
<0x0 0x20bc0000 0x0 0x40000>,
|
||||
<0x0 0x20c00000 0x0 0x40000>,
|
||||
<0x0 0x20c40000 0x0 0x40000>;
|
||||
|
||||
its: msi-controller@20840000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
reg = <0x0 0x20840000 0x0 0x40000>;
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* UART is fixed at 24MHz, both UARTCLK and PCLK.
|
||||
*/
|
||||
soc_serial0: serial@1a400000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0 0x1a400000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
watchdog@1a420000 {
|
||||
compatible = "arm,sbsa-gwdt";
|
||||
reg = <0x0 0x1a420000 0x0 0x10000>,
|
||||
<0x0 0x1a430000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
rtc@300d0000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x0 0x300d0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_clk24mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
mbox_db_tx: mailbox@40020000 {
|
||||
compatible = "arm,mhuv3";
|
||||
reg = <0x0 0x40020000 0x0 0x30000>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "combined";
|
||||
clocks = <&soc_clk24mhz>;
|
||||
#mbox-cells = <3>;
|
||||
};
|
||||
|
||||
mbox_db_rx: mailbox@40060000 {
|
||||
compatible = "arm,mhuv3";
|
||||
reg = <0x0 0x40060000 0x0 0x30000>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "combined";
|
||||
clocks = <&soc_clk24mhz>;
|
||||
#mbox-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user