github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-30 10:04:04 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/xe: Add caching pagetable flag

Browse Source 
Introduce device xe_caching_pt flag to selectively turn it on for
supported platforms. It allows to eliminate version check and enable
this feature for the future platforms.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patch.msgid.link/20251125153732.400766-2-zbigniew.kempczynski@intel.com
This commit is contained in:
Zbigniew Kempczyński 2025-11-25 16:37:33 +01:00 committed by Matthew Auld
parent 7f08cc5b3c
commit dacda0cf75
4 changed files with 10 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/xe/xe_bo.c
View File

@ -515,8 +515,7 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,
* non-coherent and require a CPU:WC mapping.
*/
if ((!bo->cpu_caching && bo->flags & XE_BO_FLAG_SCANOUT) ||
(xe->info.graphics_verx100 >= 1270 &&
bo->flags & XE_BO_FLAG_PAGETABLE))
(!xe->info.has_cached_pt && bo->flags & XE_BO_FLAG_PAGETABLE))
caching = ttm_write_combined;
}

2
drivers/gpu/drm/xe/xe_device_types.h
View File

@ -285,6 +285,8 @@ struct xe_device {
u8 has_asid:1;
/** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */
u8 has_atomic_enable_pte_bit:1;
/** @info.has_cached_pt: Supports caching pagetable */
u8 has_cached_pt:1;
/** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
u8 has_device_atomics_on_smem:1;
/** @info.has_fan_control: Device supports fan control */

6
drivers/gpu/drm/xe/xe_pci.c
View File

@ -168,6 +168,7 @@ static const struct xe_device_desc tgl_desc = {
.pre_gmdid_media_ip = &media_ip_xem,
PLATFORM(TIGERLAKE),
.dma_mask_size = 39,
.has_cached_pt = true,
.has_display = true,
.has_llc = true,
.has_sriov = true,
@ -182,6 +183,7 @@ static const struct xe_device_desc rkl_desc = {
.pre_gmdid_media_ip = &media_ip_xem,
PLATFORM(ROCKETLAKE),
.dma_mask_size = 39,
.has_cached_pt = true,
.has_display = true,
.has_llc = true,
.max_gt_per_tile = 1,
@ -197,6 +199,7 @@ static const struct xe_device_desc adl_s_desc = {
.pre_gmdid_media_ip = &media_ip_xem,
PLATFORM(ALDERLAKE_S),
.dma_mask_size = 39,
.has_cached_pt = true,
.has_display = true,
.has_llc = true,
.has_sriov = true,
@ -217,6 +220,7 @@ static const struct xe_device_desc adl_p_desc = {
.pre_gmdid_media_ip = &media_ip_xem,
PLATFORM(ALDERLAKE_P),
.dma_mask_size = 39,
.has_cached_pt = true,
.has_display = true,
.has_llc = true,
.has_sriov = true,
@ -235,6 +239,7 @@ static const struct xe_device_desc adl_n_desc = {
.pre_gmdid_media_ip = &media_ip_xem,
PLATFORM(ALDERLAKE_N),
.dma_mask_size = 39,
.has_cached_pt = true,
.has_display = true,
.has_llc = true,
.has_sriov = true,
@ -663,6 +668,7 @@ static int xe_info_init_early(struct xe_device *xe,
xe->info.vram_flags = desc->vram_flags;
xe->info.is_dgfx = desc->is_dgfx;
xe->info.has_cached_pt = desc->has_cached_pt;
xe->info.has_fan_control = desc->has_fan_control;
/* runtime fusing may force flat_ccs to disabled later */
xe->info.has_flat_ccs = desc->has_flat_ccs;

1
drivers/gpu/drm/xe/xe_pci_types.h
View File

@ -37,6 +37,7 @@ struct xe_device_desc {
u8 require_force_probe:1;
u8 is_dgfx:1;
u8 has_cached_pt:1;
u8 has_display:1;
u8 has_fan_control:1;
u8 has_flat_ccs:1;