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pinctrl: renesas: rzg2l: Update OEN pin validation to use exact match

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The RZ/G2L SoC uses pin 0 from a port for OEN while RZ/G3L uses pin 1. The
existing greater-than comparison against oen_max_pin in
rzg2l_pin_to_oen_bit() would incorrectly accept any pin below that value
rather than enforcing the single valid OEN pin for each SoC. Replace the
range check with an exact equality test so that only the designated OEN
pin is accepted.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430093422.74812-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2026-04-30 10:34:09 +01:00 committed by Geert Uytterhoeven
parent bbe2277ded
commit da4a37540b
1 changed files with 1 additions and 1 deletions
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2
drivers/pinctrl/renesas/pinctrl-rzg2l.c
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@ -1124,7 +1124,7 @@ static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data);
u8 pin = RZG2L_PIN_ID_TO_PIN(_pin);
if (pin > pctrl->data->hwcfg->oen_max_pin)
if (pin != pctrl->data->hwcfg->oen_max_pin)
return -EINVAL;
/*