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arm64: zynqmp: Move clock node to zynqmp-clk-ccf.dtsi

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Using clock firmware driver is not the only one option how to configure
clock. In past fixed clocks were also used and that configuration is still
valid that's why move clock firmware node to the same file where zynqmp_clk
references are used.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/48bfd8cf0de4d10b9c4d745218595f28954f70d5.1623684253.git.michal.simek@xilinx.com
This commit is contained in:
Michal Simek 2021-06-14 17:25:24 +02:00
parent bef1e3f5e4
commit da2618b5ae
2 changed files with 12 additions and 16 deletions
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13
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
View File

@ -2,7 +2,7 @@
/*
* Clock specification for Xilinx ZynqMP
*
* (C) Copyright 2017 - 2019, Xilinx, Inc.
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -40,6 +40,17 @@ aux_ref_clk: aux_ref_clk {
};
};
&zynqmp_firmware {
zynqmp_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
<&aux_ref_clk>, <&gt_crx_ref_clk>;
clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
"aux_ref_clk", "gt_crx_ref_clk";
};
};
&can0 {
clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
};

15
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View File

@ -156,21 +156,6 @@ zynqmp_power: zynqmp-power {
mbox-names = "tx", "rx";
};
zynqmp_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <&pss_ref_clk>,
<&video_clk>,
<&pss_alt_ref_clk>,
<&aux_ref_clk>,
<&gt_crx_ref_clk>;
clock-names = "pss_ref_clk",
"video_clk",
"pss_alt_ref_clk",
"aux_ref_clk",
"gt_crx_ref_clk";
};
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;