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dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible

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The Allwinner A523 SoC family has a second Ethernet controller, called
the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for
numbering. This controller, according to BSP sources, is fully
compatible with a slightly newer version of the Synopsys DWMAC core.
The glue layer around the controller is the same as found around older
DWMAC cores on Allwinner SoCs. The only slight difference is that since
this is the second controller on the SoC, the register for the clock
delay controls is at a different offset. Last, the integration includes
a dedicated clock gate for the memory bus and the whole thing is put in
a separately controllable power domain.

Add a compatible string entry for it, and work in the requirements for
a second clock and a power domain.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Link: https://patch.msgid.link/20250925191600.3306595-2-wens@kernel.org
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Chen-Yu Tsai 2025-09-26 03:15:58 +08:00 committed by Paolo Abeni
parent 1a98f5699b
commit d9fcb34f8b
1 changed files with 93 additions and 2 deletions
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95
Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
View File

@ -10,6 +10,21 @@ maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
# We need a select here so we don't match all nodes with 'snps,dwmac'
select:
properties:
compatible:
contains:
enum:
- allwinner,sun8i-a83t-emac
- allwinner,sun8i-h3-emac
- allwinner,sun8i-r40-gmac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
- allwinner,sun55i-a523-gmac200
required:
- compatible
properties:
compatible:
oneOf:
@ -26,6 +41,9 @@ properties:
- allwinner,sun50i-h616-emac0
- allwinner,sun55i-a523-gmac0
- const: allwinner,sun50i-a64-emac
- items:
- const: allwinner,sun55i-a523-gmac200
- const: snps,dwmac-4.20a
reg:
maxItems: 1
@ -37,14 +55,21 @@ properties:
const: macirq
clocks:
maxItems: 1
minItems: 1
maxItems: 2
clock-names:
const: stmmaceth
minItems: 1
items:
- const: stmmaceth
- const: mbus
phy-supply:
description: PHY regulator
power-domains:
maxItems: 1
syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
@ -191,6 +216,42 @@ allOf:
- mdio-parent-bus
- mdio@1
- if:
properties:
compatible:
contains:
const: allwinner,sun55i-a523-gmac200
then:
properties:
clocks:
minItems: 2
clock-names:
minItems: 2
tx-internal-delay-ps:
default: 0
minimum: 0
maximum: 700
multipleOf: 100
description:
External RGMII PHY TX clock delay chain value in ps.
rx-internal-delay-ps:
default: 0
minimum: 0
maximum: 3100
multipleOf: 100
description:
External RGMII PHY TX clock delay chain value in ps.
required:
- power-domains
else:
properties:
clocks:
maxItems: 1
clock-names:
maxItems: 1
power-domains: false
unevaluatedProperties: false
examples:
@ -323,4 +384,34 @@ examples:
};
};
- |
ethernet@4510000 {
compatible = "allwinner,sun55i-a523-gmac200",
"snps,dwmac-4.20a";
reg = <0x04510000 0x10000>;
clocks = <&ccu 117>, <&ccu 79>;
clock-names = "stmmaceth", "mbus";
resets = <&ccu 43>;
reset-names = "stmmaceth";
interrupts = <0 47 4>;
interrupt-names = "macirq";
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins>;
power-domains = <&pck600 4>;
syscon = <&syscon>;
phy-handle = <&ext_rgmii_phy_1>;
phy-mode = "rgmii-id";
snps,fixed-burst;
snps,axi-config = <&gmac1_stmmac_axi_setup>;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ext_rgmii_phy_1: ethernet-phy@1 {
reg = <1>;
};
};
};
...