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Merge branch 'pci/controller/speed'
- Use PCIE_SPEED2MBS_ENC() macro in qcom host and endpoint to encode link speed instead of hard-coding the link speed in MBps (Manivannan Sadhasivam) - Use Mbps_to_icc() (not MBps_to_icc()) in tegra194 instead of explicitly doing the bytes-to-bits conversion (Manivannan Sadhasivam) * pci/controller/speed: PCI: tegra194: Use Mbps_to_icc() macro for setting icc speed PCI: qcom-ep: Use PCIE_SPEED2MBS_ENC() macro for encoding link speed PCI: qcom: Use PCIE_SPEED2MBS_ENC() macro for encoding link speed
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commit
d97ab9e533
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@ -23,6 +23,7 @@
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#include <linux/reset.h>
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#include <linux/module.h>
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#include "../../pci.h"
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#include "pcie-designware.h"
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/* PARF registers */
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@ -136,10 +137,8 @@
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#define CORE_RESET_TIME_US_MAX 1005
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#define WAKE_DELAY_US 2000 /* 2 ms */
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#define PCIE_GEN1_BW_MBPS 250
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#define PCIE_GEN2_BW_MBPS 500
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#define PCIE_GEN3_BW_MBPS 985
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#define PCIE_GEN4_BW_MBPS 1969
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#define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \
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Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]))
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#define to_pcie_ep(x) dev_get_drvdata((x)->dev)
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@ -282,7 +281,7 @@ static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base,
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static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)
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{
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struct dw_pcie *pci = &pcie_ep->pci;
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u32 offset, status, bw;
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u32 offset, status;
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int speed, width;
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int ret;
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@ -295,25 +294,7 @@ static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)
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speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
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width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
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switch (speed) {
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case 1:
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bw = MBps_to_icc(PCIE_GEN1_BW_MBPS);
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break;
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case 2:
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bw = MBps_to_icc(PCIE_GEN2_BW_MBPS);
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break;
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case 3:
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bw = MBps_to_icc(PCIE_GEN3_BW_MBPS);
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break;
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default:
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dev_warn(pci->dev, "using default GEN4 bandwidth\n");
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fallthrough;
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case 4:
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bw = MBps_to_icc(PCIE_GEN4_BW_MBPS);
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break;
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}
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ret = icc_set_bw(pcie_ep->icc_mem, 0, width * bw);
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ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
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if (ret)
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dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
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ret);
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@ -351,7 +332,7 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
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* Set an initial peak bandwidth corresponding to single-lane Gen 1
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* for the pcie-mem path.
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*/
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ret = icc_set_bw(pcie_ep->icc_mem, 0, MBps_to_icc(PCIE_GEN1_BW_MBPS));
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ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
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if (ret) {
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dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
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ret);
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@ -148,6 +148,9 @@
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#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0))
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#define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \
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Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]))
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#define QCOM_PCIE_1_0_0_MAX_CLOCKS 4
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struct qcom_pcie_resources_1_0_0 {
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struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS];
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@ -1375,7 +1378,7 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
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* Set an initial peak bandwidth corresponding to single-lane Gen 1
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* for the pcie-mem path.
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*/
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ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250));
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ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
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if (ret) {
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dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
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ret);
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@ -1388,7 +1391,7 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
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static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
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{
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struct dw_pcie *pci = pcie->pci;
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u32 offset, status, bw;
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u32 offset, status;
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int speed, width;
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int ret;
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@ -1405,22 +1408,7 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
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speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
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width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
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switch (speed) {
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case 1:
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bw = MBps_to_icc(250);
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break;
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case 2:
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bw = MBps_to_icc(500);
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break;
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default:
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WARN_ON_ONCE(1);
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fallthrough;
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case 3:
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bw = MBps_to_icc(985);
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break;
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}
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ret = icc_set_bw(pcie->icc_mem, 0, width * bw);
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ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
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if (ret) {
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dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
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ret);
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@ -321,9 +321,9 @@ static void tegra_pcie_icc_set(struct tegra_pcie_dw *pcie)
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speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, val);
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width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val);
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val = width * (PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]) / BITS_PER_BYTE);
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val = width * PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]);
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if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0))
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if (icc_set_bw(pcie->icc_path, Mbps_to_icc(val), 0))
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dev_err(pcie->dev, "can't set bw[%u]\n", val);
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if (speed >= ARRAY_SIZE(pcie_gen_freq))
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