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dt-bindings: memory: Add Tegra234 support
This stable tag contains the addition of the EMC clock ID and an initial list of memory client IDs for Tegra234 and will be shared between the memory and ARM SoC trees. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmG7X0wTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoYnaEACCu8X8EkUCFJmu3wdy3CZl5qRscxoH rBo99Tg2vwKhjtOa25POQJIZsTaCN4CprgAxP/6ziOPNX+n+BjGnhs0fPoep+4H/ nx6k2l4gDBN3BrrauBHJzoGoOJ/mM0phdJwL3LtPfDMNqjR/SbrTya1zACRSB4iJ 9nDs0Hw98iO4sTtTfQrvS5SEQSim44QjwoQY89St2dMrZGgk5S70A8F9LKbsyI+P KyOjfuUvOyyORHaSE7det0KwwPSApz9khsQ9ikhv2TGoX4hgadEL0O8db7Oha/kH sMVW3vCiFRL8t6KwQSHiX1jso0tEKTEEqloMB5QwnByx49F4OWbwCfp8TvJACmJL Fbfu8VzlExryhUjq4X5zzRWeWJjeInBAqSHk7z20Zl1NNDPYUO/IRvYe3yR0o+s9 OdJ8AP0kIJRRwnubJJ74oam/VzzygRhRJuCoZowoJuECseUHi0T09dNwms92N8xT H9peVdxZiLL5EAT7WBPrlHzM27/YEzBVj8uwgawouZwgYs3tpYrev4qEno4wc/In JPXTY2xIenMphPH4vU0v/ZW1G2TDtgWQpY+U2beXmquHvgBvkrQphvaaDfOSDohV EnO+F1ISQ7kIFGlX1eH59GnkUiMw10T4JpQ5nc70sVME/Kp4/aAiDEu5CB0lGEaP 2JOkCHpzCa1sOQ== =bl4k -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.17-dt-bindings-memory' into for-5.17/arm64/dt dt-bindings: memory: Add Tegra234 support This stable tag contains the addition of the EMC clock ID and an initial list of memory client IDs for Tegra234 and will be shared between the memory and ARM SoC trees.
This commit is contained in:
Thierry Reding
commit
d9652f589e
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@ -31,12 +31,15 @@ properties:
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- enum:
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- nvidia,tegra186-mc
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- nvidia,tegra194-mc
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- nvidia,tegra234-mc
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reg:
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maxItems: 1
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minItems: 1
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maxItems: 3
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interrupts:
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maxItems: 1
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items:
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- description: MC general interrupt
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"#address-cells":
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const: 2
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@ -48,6 +51,9 @@ properties:
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dma-ranges: true
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"#interconnect-cells":
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const: 1
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patternProperties:
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"^external-memory-controller@[0-9a-f]+$":
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description:
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@ -63,12 +69,15 @@ patternProperties:
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- enum:
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- nvidia,tegra186-emc
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- nvidia,tegra194-emc
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- nvidia,tegra234-emc
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reg:
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maxItems: 1
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minItems: 1
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maxItems: 2
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interrupts:
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maxItems: 1
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items:
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- description: EMC general interrupt
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clocks:
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items:
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@ -78,11 +87,83 @@ patternProperties:
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items:
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- const: emc
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"#interconnect-cells":
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const: 0
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nvidia,bpmp:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle of the node representing the BPMP
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allOf:
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- if:
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properties:
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compatible:
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const: nvidia,tegra186-emc
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then:
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properties:
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reg:
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maxItems: 1
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- if:
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properties:
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compatible:
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const: nvidia,tegra194-emc
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then:
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properties:
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reg:
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minItems: 2
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- if:
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properties:
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compatible:
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const: nvidia,tegra234-emc
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then:
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properties:
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reg:
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minItems: 2
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- "#interconnect-cells"
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- nvidia,bpmp
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allOf:
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- if:
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properties:
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compatible:
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const: nvidia,tegra186-mc
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then:
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properties:
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reg:
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maxItems: 1
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- if:
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properties:
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compatible:
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const: nvidia,tegra194-mc
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then:
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properties:
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reg:
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minItems: 3
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- if:
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properties:
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compatible:
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const: nvidia,tegra234-mc
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then:
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properties:
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reg:
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minItems: 3
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additionalProperties: false
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required:
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- compatible
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- reg
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@ -90,8 +171,6 @@ required:
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- "#address-cells"
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- "#size-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/tegra186-clock.h>
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@ -124,12 +203,9 @@ examples:
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clocks = <&bpmp TEGRA186_CLK_EMC>;
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clock-names = "emc";
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#interconnect-cells = <0>;
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nvidia,bpmp = <&bpmp>;
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};
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};
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};
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bpmp: bpmp {
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compatible = "nvidia,tegra186-bpmp";
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#clock-cells = <1>;
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};
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@ -4,11 +4,31 @@
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#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
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#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
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/**
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* @file
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* @defgroup bpmp_clock_ids Clock ID's
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* @{
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*/
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/**
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* @brief controls the EMC clock frequency.
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* @details Doing a clk_set_rate on this clock will select the
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* appropriate clock source, program the source rate and execute a
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* specific sequence to switch to the new clock source for both memory
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* controllers. This can be used to control the balance between memory
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* throughput and memory controller power.
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*/
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#define TEGRA234_CLK_EMC 31U
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/** @brief output of gate CLK_ENB_FUSE */
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#define TEGRA234_CLK_FUSE 40
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#define TEGRA234_CLK_FUSE 40U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
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#define TEGRA234_CLK_SDMMC4 123
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#define TEGRA234_CLK_SDMMC4 123U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
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#define TEGRA234_CLK_UARTA 155
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#define TEGRA234_CLK_UARTA 155U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
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#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U
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/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
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#define TEGRA234_CLK_PLLC4 237U
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/** @brief 32K input clock provided by PMIC */
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#define TEGRA234_CLK_CLK_32K 289U
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#endif
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32
include/dt-bindings/memory/tegra234-mc.h
Normal file
32
include/dt-bindings/memory/tegra234-mc.h
Normal file
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@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA234_MC_H
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/* special clients */
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#define TEGRA234_SID_INVALID 0x00
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#define TEGRA234_SID_PASSTHROUGH 0x7f
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/* NISO1 stream IDs */
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#define TEGRA234_SID_SDMMC4 0x02
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#define TEGRA234_SID_BPMP 0x10
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/*
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* memory client IDs
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*/
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/* sdmmcd memory read client */
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#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
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/* sdmmcd memory write client */
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#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
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/* BPMP read client */
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#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93
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/* BPMP write client */
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#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94
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/* BPMPDMA read client */
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#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95
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/* BPMPDMA write client */
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#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96
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#endif
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@ -4,7 +4,15 @@
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#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
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#define DT_BINDINGS_RESET_TEGRA234_RESET_H
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#define TEGRA234_RESET_SDMMC4 85
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#define TEGRA234_RESET_UARTA 100
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/**
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* @file
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* @defgroup bpmp_reset_ids Reset ID's
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* @brief Identifiers for Resets controllable by firmware
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* @{
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*/
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#define TEGRA234_RESET_SDMMC4 85U
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#define TEGRA234_RESET_UARTA 100U
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/** @} */
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#endif
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