drm/amd/ras: rename core ras_* files and update include guards

Rename selected RAS core source and header filenames to drop
redundant ras_ prefixes in file names only.

Update related build object names, header include references, and
include guard macros in renamed headers.

Function/type prefixes and runtime behavior are unchanged.

No functional change intended.

Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/ras/core/Makefile

@@ -19,25 +19,25 @@
 # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 # OTHER DEALINGS IN THE SOFTWARE.
 #
-RAS_CORE_FILES = ras_core.o \
+RAS_CORE_FILES = core.o \
 			ras_mp1.o \
 			ras_mp1_v13_0.o \
-			ras_aca.o  \
-			ras_aca_v1_0.o \
-			ras_eeprom.o \
+			aca.o  \
+			aca_v1_0.o \
+			eeprom.o \
 			ras_umc.o \
 			ras_umc_v12_0.o \
-			ras_cmd.o \
+			cmd.o \
 			ras_gfx.o \
 			ras_gfx_v9_0.o \
 			ras_process.o \
 			ras_nbio.o \
 			ras_nbio_v7_9.o \
-			ras_log_ring.o \
+			log_ring.o \
 			ras_cper.o \
 			ras_psp.o \
 			ras_psp_v13_0.o \
-			ras_eeprom_fw.o
+			eeprom_fw.o
 
 
 RAS_CORE = $(addprefix $(AMD_GPU_RAS_PATH)/core/,$(RAS_CORE_FILES))

drivers/gpu/drm/amd/ras/core/aca.c

@@ -22,8 +22,8 @@
  *
  */
 #include "ras.h"
-#include "ras_aca.h"
-#include "ras_aca_v1_0.h"
+#include "aca.h"
+#include "aca_v1_0.h"
 #include "ras_mp1_v13_0.h"
 
 #define ACA_MARK_FATAL_FLAG    0x100

drivers/gpu/drm/amd/ras/core/aca.h

@@ -22,8 +22,8 @@
  *
  */
 
-#ifndef __RAS_ACA_H__
-#define __RAS_ACA_H__
+#ifndef __ACA_H__
+#define __ACA_H__
 #include "ras.h"
 
 #define MAX_SOCKET_NUM_PER_HIVE 8

drivers/gpu/drm/amd/ras/core/aca_v1_0.c

@@ -22,9 +22,9 @@
  *
  */
 #include "ras.h"
-#include "ras_aca.h"
-#include "ras_core_status.h"
-#include "ras_aca_v1_0.h"
+#include "aca.h"
+#include "core_status.h"
+#include "aca_v1_0.h"
 
 struct ras_aca_hwip {
 	int hwid;

drivers/gpu/drm/amd/ras/core/aca_v1_0.h

@@ -22,8 +22,8 @@
  *
  */
 
-#ifndef __RAS_ACA_V1_0_H__
-#define __RAS_ACA_V1_0_H__
+#ifndef __ACA_V1_0_H__
+#define __ACA_V1_0_H__
 #include "ras.h"
 
 #define ACA__REG__FIELD(x, h, l)		  (((x) & GENMASK_ULL(h, l)) >> l)

drivers/gpu/drm/amd/ras/core/cmd.c

@@ -22,7 +22,7 @@
  *
  */
 #include "ras.h"
-#include "ras_cmd.h"
+#include "cmd.h"
 
 #define RAS_CMD_MAJOR_VERSION 6
 #define RAS_CMD_MINOR_VERSION 0

drivers/gpu/drm/amd/ras/core/cmd.h

@@ -22,11 +22,11 @@
  *
  */
 
-#ifndef __RAS_CMD_H__
-#define __RAS_CMD_H__
+#ifndef __CMD_H__
+#define __CMD_H__
 #include "ras.h"
-#include "ras_eeprom.h"
-#include "ras_log_ring.h"
+#include "eeprom.h"
+#include "log_ring.h"
 #include "ras_cper.h"
 
 #define RAS_CMD_MAX_IN_SIZE 256

drivers/gpu/drm/amd/ras/core/core.c

@@ -22,7 +22,7 @@
  *
  */
 #include "ras.h"
-#include "ras_core_status.h"
+#include "core_status.h"
 
 #define RAS_SEQNO_FIFO_SIZE (128 * sizeof(uint64_t))
 

drivers/gpu/drm/amd/ras/core/core_status.h

@@ -22,8 +22,8 @@
  *
  */
 
-#ifndef __RAS_CORE_STATUS_H__
-#define __RAS_CORE_STATUS_H__
+#ifndef __CORE_STATUS_H__
+#define __CORE_STATUS_H__
 
 #define RAS_CORE_OK                       0
 #define RAS_CORE_NOT_SUPPORTED            248

drivers/gpu/drm/amd/ras/core/eeprom.c

@@ -22,7 +22,7 @@
  *
  */
 
-#include "ras_eeprom.h"
+#include "eeprom.h"
 #include "ras.h"
 
 /* These are memory addresses as would be seen by one or more EEPROM

drivers/gpu/drm/amd/ras/core/eeprom.h

@@ -22,8 +22,8 @@
  *
  */
 
-#ifndef __RAS_EEPROM_H__
-#define __RAS_EEPROM_H__
+#ifndef __EEPROM_H__
+#define __EEPROM_H__
 #include "ras_sys.h"
 
 #define RAS_TABLE_VER_V1           0x00010000

drivers/gpu/drm/amd/ras/core/eeprom_fw.h

@@ -21,8 +21,8 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  */
-#ifndef __RAS_EEPROM_FW_H__
-#define __RAS_EEPROM_FW_H__
+#ifndef __EEPROM_FW_H__
+#define __EEPROM_FW_H__
 
 struct ras_fw_eeprom_control {
 	uint32_t version;

drivers/gpu/drm/amd/ras/core/log_ring.c

@@ -22,8 +22,8 @@
  *
  */
 #include "ras.h"
-#include "ras_core_status.h"
-#include "ras_log_ring.h"
+#include "core_status.h"
+#include "log_ring.h"
 
 #define RAS_LOG_MAX_QUERY_SIZE   0xC000
 #define RAS_LOG_MEM_TEMP_SIZE    0x200

drivers/gpu/drm/amd/ras/core/log_ring.h

@@ -21,9 +21,9 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  */
-#ifndef __RAS_LOG_RING_H__
-#define __RAS_LOG_RING_H__
-#include "ras_aca.h"
+#ifndef __LOG_RING_H__
+#define __LOG_RING_H__
+#include "aca.h"
 
 #define MAX_RECORD_PER_BATCH 32
 

drivers/gpu/drm/amd/ras/core/ras.h

@@ -26,17 +26,17 @@
 #define __RAS_H__
 #include "ras_sys.h"
 #include "ras_umc.h"
-#include "ras_aca.h"
-#include "ras_eeprom.h"
-#include "ras_core_status.h"
+#include "aca.h"
+#include "eeprom.h"
+#include "core_status.h"
 #include "ras_process.h"
 #include "ras_gfx.h"
-#include "ras_cmd.h"
+#include "cmd.h"
 #include "ras_nbio.h"
 #include "ras_mp1.h"
 #include "ras_psp.h"
-#include "ras_log_ring.h"
-#include "ras_eeprom_fw.h"
+#include "log_ring.h"
+#include "eeprom_fw.h"
 
 #define RAS_HW_ERR		"[Hardware Error]: "
 

drivers/gpu/drm/amd/ras/core/ras_cper.c

@@ -22,8 +22,8 @@
  *
  */
 #include "ras.h"
-#include "ras_core_status.h"
-#include "ras_log_ring.h"
+#include "core_status.h"
+#include "log_ring.h"
 #include "ras_cper.h"
 
 static const struct ras_cper_guid MCE	= CPER_NOTIFY__MCE;

drivers/gpu/drm/amd/ras/core/ras_gfx.c

@@ -25,7 +25,7 @@
 #include "ras.h"
 #include "ras_gfx_v9_0.h"
 #include "ras_gfx.h"
-#include "ras_core_status.h"
+#include "core_status.h"
 
 static const struct ras_gfx_ip_func *ras_gfx_get_ip_funcs(
 				struct ras_core_context *ras_core, uint32_t ip_version)

drivers/gpu/drm/amd/ras/core/ras_gfx_v9_0.c

@@ -23,7 +23,7 @@
  */
 #include "ras.h"
 #include "ras_gfx_v9_0.h"
-#include "ras_core_status.h"
+#include "core_status.h"
 
 enum ta_gfx_v9_subblock {
 	/*CPC*/

drivers/gpu/drm/amd/ras/core/ras_mp1_v13_0.c

@@ -23,7 +23,7 @@
  */
 #include "ras.h"
 #include "ras_mp1.h"
-#include "ras_core_status.h"
+#include "core_status.h"
 #include "ras_mp1_v13_0.h"
 
 #define RAS_MP1_MSG_QueryValidMcaCount                0x36

drivers/gpu/drm/amd/ras/core/ras_psp.c

@@ -22,7 +22,7 @@
  *
  */
 #include "ras.h"
-#include "ras_ta_if.h"
+#include "ta_if.h"
 #include "ras_psp.h"
 #include "ras_psp_v13_0.h"
 

drivers/gpu/drm/amd/ras/core/ras_psp.h

@@ -24,7 +24,7 @@
 #ifndef __RAS_PSP_H__
 #define __RAS_PSP_H__
 #include "ras.h"
-#include "ras_ta_if.h"
+#include "ta_if.h"
 
 struct ras_core_context;
 struct ras_ta_trigger_error_input;

drivers/gpu/drm/amd/ras/core/ras_umc.h

@@ -25,8 +25,8 @@
 #ifndef __RAS_UMC_H__
 #define __RAS_UMC_H__
 #include "ras.h"
-#include "ras_eeprom.h"
-#include "ras_cmd.h"
+#include "eeprom.h"
+#include "cmd.h"
 
 #define UMC_VRAM_TYPE_UNKNOWN 0
 #define UMC_VRAM_TYPE_GDDR1   1

drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.c

@@ -23,7 +23,7 @@
  */
 #include "ras.h"
 #include "ras_umc.h"
-#include "ras_core_status.h"
+#include "core_status.h"
 #include "ras_umc_v12_0.h"
 
 #define NumDieInterleaved 4

drivers/gpu/drm/amd/ras/core/ta_if.h

@@ -22,8 +22,8 @@
  *
  */
 
-#ifndef _RAS_TA_IF_H
-#define _RAS_TA_IF_H
+#ifndef _TA_IF_H
+#define _TA_IF_H
 #include "ras.h"
 
 #define RAS_TA_HOST_IF_VER	0

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.c

@@ -26,7 +26,7 @@
 #include "amdgpu_ras_eeprom.h"
 #include "amdgpu_ras_mgr.h"
 #include "amdgpu_ras_eeprom_i2c.h"
-#include "ras_eeprom.h"
+#include "eeprom.h"
 
 /* These are memory addresses as would be seen by one or more EEPROM
  * chips strung on the I2C bus, usually by manipulating pins 1-3 of a