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drm/i915/gmbus: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain point in the register access macros I915_READ(), I915_WRITE(), POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW(). Replace them with the corresponding new display engine register accessors intel_de_read(), intel_de_write(), intel_de_posting_read(), intel_de_read_fw(), and intel_de_write_fw(). No functional changes. Generated using the following semantic patch: @@ expression REG, OFFSET; @@ - I915_READ(REG) + intel_de_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - POSTING_READ(REG) + intel_de_posting_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE(REG, OFFSET) + intel_de_write(dev_priv, REG, OFFSET) @@ expression REG; @@ - I915_READ_FW(REG) + intel_de_read_fw(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE_FW(REG, OFFSET) + intel_de_write_fw(dev_priv, REG, OFFSET) Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1fca6f7e201fb2c75fcfff213ebd982a988eb40d.1579871655.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula
parent
f639c497ae
commit
d9053b237b
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@ -143,8 +143,8 @@ to_intel_gmbus(struct i2c_adapter *i2c)
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void
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intel_gmbus_reset(struct drm_i915_private *dev_priv)
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{
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I915_WRITE(GMBUS0, 0);
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I915_WRITE(GMBUS4, 0);
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intel_de_write(dev_priv, GMBUS0, 0);
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intel_de_write(dev_priv, GMBUS4, 0);
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}
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static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
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@ -153,12 +153,12 @@ static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
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u32 val;
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/* When using bit bashing for I2C, this bit needs to be set to 1 */
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val = I915_READ(DSPCLK_GATE_D);
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val = intel_de_read(dev_priv, DSPCLK_GATE_D);
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if (!enable)
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val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
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else
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val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(DSPCLK_GATE_D, val);
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intel_de_write(dev_priv, DSPCLK_GATE_D, val);
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}
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static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
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@ -166,12 +166,12 @@ static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
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{
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u32 val;
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val = I915_READ(SOUTH_DSPCLK_GATE_D);
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val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);
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if (!enable)
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val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
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else
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val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
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intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);
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}
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static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
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@ -179,12 +179,12 @@ static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
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{
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u32 val;
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val = I915_READ(GEN9_CLKGATE_DIS_4);
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val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4);
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if (!enable)
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val |= BXT_GMBUS_GATING_DIS;
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else
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val &= ~BXT_GMBUS_GATING_DIS;
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I915_WRITE(GEN9_CLKGATE_DIS_4, val);
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intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val);
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}
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static u32 get_reserved(struct intel_gmbus *bus)
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@ -337,14 +337,16 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
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irq_en = 0;
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add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
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I915_WRITE_FW(GMBUS4, irq_en);
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intel_de_write_fw(dev_priv, GMBUS4, irq_en);
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status |= GMBUS_SATOER;
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ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2);
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ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
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2);
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if (ret)
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ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50);
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ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
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50);
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I915_WRITE_FW(GMBUS4, 0);
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intel_de_write_fw(dev_priv, GMBUS4, 0);
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remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
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if (gmbus2 & GMBUS_SATOER)
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@ -366,13 +368,13 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
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irq_enable = GMBUS_IDLE_EN;
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add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
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I915_WRITE_FW(GMBUS4, irq_enable);
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intel_de_write_fw(dev_priv, GMBUS4, irq_enable);
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ret = intel_wait_for_register_fw(&dev_priv->uncore,
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GMBUS2, GMBUS_ACTIVE, 0,
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10);
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I915_WRITE_FW(GMBUS4, 0);
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intel_de_write_fw(dev_priv, GMBUS4, 0);
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remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
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return ret;
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@ -404,15 +406,12 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
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len++;
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}
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size = len % 256 + 256;
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I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
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intel_de_write_fw(dev_priv, GMBUS0,
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gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
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}
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I915_WRITE_FW(GMBUS1,
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gmbus1_index |
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GMBUS_CYCLE_WAIT |
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(size << GMBUS_BYTE_COUNT_SHIFT) |
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(addr << GMBUS_SLAVE_ADDR_SHIFT) |
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GMBUS_SLAVE_READ | GMBUS_SW_RDY);
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intel_de_write_fw(dev_priv, GMBUS1,
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gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
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while (len) {
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int ret;
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u32 val, loop = 0;
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@ -421,7 +420,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
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if (ret)
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return ret;
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val = I915_READ_FW(GMBUS3);
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val = intel_de_read_fw(dev_priv, GMBUS3);
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do {
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if (extra_byte_added && len == 1)
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break;
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@ -432,7 +431,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
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if (burst_read && len == size - 4)
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/* Reset the override bit */
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I915_WRITE_FW(GMBUS0, gmbus0_reg);
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intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg);
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}
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return 0;
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@ -489,12 +488,9 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
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len -= 1;
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}
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I915_WRITE_FW(GMBUS3, val);
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I915_WRITE_FW(GMBUS1,
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gmbus1_index | GMBUS_CYCLE_WAIT |
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(chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
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(addr << GMBUS_SLAVE_ADDR_SHIFT) |
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GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
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intel_de_write_fw(dev_priv, GMBUS3, val);
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intel_de_write_fw(dev_priv, GMBUS1,
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gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
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while (len) {
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int ret;
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@ -503,7 +499,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
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val |= *buf++ << (8 * loop);
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} while (--len && ++loop < 4);
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I915_WRITE_FW(GMBUS3, val);
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intel_de_write_fw(dev_priv, GMBUS3, val);
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ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
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if (ret)
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@ -568,7 +564,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
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/* GMBUS5 holds 16-bit index */
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if (gmbus5)
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I915_WRITE_FW(GMBUS5, gmbus5);
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intel_de_write_fw(dev_priv, GMBUS5, gmbus5);
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if (msgs[1].flags & I2C_M_RD)
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ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
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@ -578,7 +574,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
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/* Clear GMBUS5 after each index transfer */
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if (gmbus5)
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I915_WRITE_FW(GMBUS5, 0);
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intel_de_write_fw(dev_priv, GMBUS5, 0);
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return ret;
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}
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@ -601,7 +597,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
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pch_gmbus_clock_gating(dev_priv, false);
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retry:
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I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0);
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intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0);
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for (; i < num; i += inc) {
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inc = 1;
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@ -629,7 +625,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
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* a STOP on the very first cycle. To simplify the code we
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* unconditionally generate the STOP condition with an additional gmbus
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* cycle. */
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I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
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intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
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/* Mark the GMBUS interface as disabled after waiting for idle.
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* We will re-enable it at the start of the next xfer,
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@ -640,7 +636,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
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adapter->name);
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ret = -ETIMEDOUT;
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}
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I915_WRITE_FW(GMBUS0, 0);
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intel_de_write_fw(dev_priv, GMBUS0, 0);
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ret = ret ?: i;
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goto out;
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@ -669,9 +665,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
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* of resetting the GMBUS controller and so clearing the
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* BUS_ERROR raised by the slave's NAK.
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*/
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I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
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I915_WRITE_FW(GMBUS1, 0);
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I915_WRITE_FW(GMBUS0, 0);
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intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT);
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intel_de_write_fw(dev_priv, GMBUS1, 0);
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intel_de_write_fw(dev_priv, GMBUS0, 0);
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DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
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adapter->name, msgs[i].addr,
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@ -694,7 +690,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
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timeout:
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DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
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bus->adapter.name, bus->reg0 & 0xff);
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I915_WRITE_FW(GMBUS0, 0);
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intel_de_write_fw(dev_priv, GMBUS0, 0);
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/*
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* Hardware may not support GMBUS over these pins? Try GPIO bitbanging
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