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perf/x86/intel/uncore: Support IIO free-running counters on DMR
The free-running counters for IIO uncore blocks on Diamond Rapids are similar to Sapphire Rapids IMC freecounters, with the following differences: - The counters are MMIO based. - Only a subset of IP blocks implement free-running counters: HIOP0 (IP Base Addr: 2E7000h) HIOP1 (IP Base Addr: 2EF000h) HIOP3 (IP Base Addr: 2FF000h) HIOP4 (IP Base Addr: 307000h) - IMH2 (Secondary IMH) does not provide free-running counters. Signed-off-by: Zide Chen <zide.chen@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Link: https://patch.msgid.link/20251231224233.113839-9-zide.chen@intel.com
This commit is contained in:
Zide Chen
Peter Zijlstra
parent
8a4bd1c0d6
commit
d8987048f6
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@ -472,10 +472,14 @@
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#define SPR_C0_MSR_PMON_BOX_FILTER0 0x200e
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#define SPR_C0_MSR_PMON_BOX_FILTER0 0x200e
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/* DMR */
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/* DMR */
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#define DMR_IMH1_HIOP_MMIO_BASE 0x1ffff6ae7000
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#define DMR_HIOP_MMIO_SIZE 0x8000
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#define DMR_CXLCM_EVENT_MASK_EXT 0xf
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#define DMR_CXLCM_EVENT_MASK_EXT 0xf
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#define DMR_HAMVF_EVENT_MASK_EXT 0xffffffff
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#define DMR_HAMVF_EVENT_MASK_EXT 0xffffffff
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#define DMR_PCIE4_EVENT_MASK_EXT 0xffffff
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#define DMR_PCIE4_EVENT_MASK_EXT 0xffffff
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#define UNCORE_DMR_ITC 0x30
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#define DMR_IMC_PMON_FIXED_CTR 0x18
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#define DMR_IMC_PMON_FIXED_CTR 0x18
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#define DMR_IMC_PMON_FIXED_CTL 0x10
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#define DMR_IMC_PMON_FIXED_CTL 0x10
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@ -6442,7 +6446,11 @@ static int uncore_type_max_boxes(struct intel_uncore_type **types,
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for (node = rb_first(type->boxes); node; node = rb_next(node)) {
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for (node = rb_first(type->boxes); node; node = rb_next(node)) {
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unit = rb_entry(node, struct intel_uncore_discovery_unit, node);
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unit = rb_entry(node, struct intel_uncore_discovery_unit, node);
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if (unit->id > max)
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/*
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* on DMR IMH2, the unit id starts from 0x8000,
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* and we don't need to count it.
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*/
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if ((unit->id > max) && (unit->id < 0x8000))
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max = unit->id;
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max = unit->id;
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}
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}
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return max + 1;
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return max + 1;
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@ -6930,6 +6938,101 @@ int dmr_uncore_cbb_units_ignore[] = {
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UNCORE_IGNORE_END
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UNCORE_IGNORE_END
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};
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};
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static unsigned int dmr_iio_freerunning_box_offsets[] = {
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0x0, 0x8000, 0x18000, 0x20000
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};
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static void dmr_uncore_freerunning_init_box(struct intel_uncore_box *box)
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{
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struct intel_uncore_type *type = box->pmu->type;
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u64 mmio_base;
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if (box->pmu->pmu_idx >= type->num_boxes)
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return;
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mmio_base = DMR_IMH1_HIOP_MMIO_BASE;
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mmio_base += dmr_iio_freerunning_box_offsets[box->pmu->pmu_idx];
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box->io_addr = ioremap(mmio_base, type->mmio_map_size);
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if (!box->io_addr)
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pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name);
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}
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static struct intel_uncore_ops dmr_uncore_freerunning_ops = {
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.init_box = dmr_uncore_freerunning_init_box,
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.exit_box = uncore_mmio_exit_box,
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.read_counter = uncore_mmio_read_counter,
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.hw_config = uncore_freerunning_hw_config,
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};
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enum perf_uncore_dmr_iio_freerunning_type_id {
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DMR_ITC_INB_DATA_BW,
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DMR_ITC_BW_IN,
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DMR_OTC_BW_OUT,
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DMR_OTC_CLOCK_TICKS,
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DMR_IIO_FREERUNNING_TYPE_MAX,
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};
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static struct freerunning_counters dmr_iio_freerunning[] = {
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[DMR_ITC_INB_DATA_BW] = { 0x4d40, 0x8, 0, 8, 48},
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[DMR_ITC_BW_IN] = { 0x6b00, 0x8, 0, 8, 48},
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[DMR_OTC_BW_OUT] = { 0x6b60, 0x8, 0, 8, 48},
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[DMR_OTC_CLOCK_TICKS] = { 0x6bb0, 0x8, 0, 1, 48},
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};
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static struct uncore_event_desc dmr_uncore_iio_freerunning_events[] = {
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/* ITC Free Running Data BW counter for inbound traffic */
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INTEL_UNCORE_FR_EVENT_DESC(inb_data_port0, 0x10, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(inb_data_port1, 0x11, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(inb_data_port2, 0x12, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(inb_data_port3, 0x13, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(inb_data_port4, 0x14, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(inb_data_port5, 0x15, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(inb_data_port6, 0x16, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(inb_data_port7, 0x17, "3.814697266e-6"),
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/* ITC Free Running BW IN counters */
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INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(bw_in_port4, 0x24, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(bw_in_port5, 0x25, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(bw_in_port6, 0x26, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(bw_in_port7, 0x27, "3.814697266e-6"),
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/* ITC Free Running BW OUT counters */
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INTEL_UNCORE_FR_EVENT_DESC(bw_out_port0, 0x30, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(bw_out_port1, 0x31, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(bw_out_port2, 0x32, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(bw_out_port3, 0x33, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(bw_out_port4, 0x34, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(bw_out_port5, 0x35, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(bw_out_port6, 0x36, "3.814697266e-6"),
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INTEL_UNCORE_FR_EVENT_DESC(bw_out_port7, 0x37, "3.814697266e-6"),
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/* Free Running Clock Counter */
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INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x40"),
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{ /* end: all zeroes */ },
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};
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static struct intel_uncore_type dmr_uncore_iio_free_running = {
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.name = "iio_free_running",
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.num_counters = 25,
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.mmio_map_size = DMR_HIOP_MMIO_SIZE,
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.num_freerunning_types = DMR_IIO_FREERUNNING_TYPE_MAX,
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.freerunning = dmr_iio_freerunning,
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.ops = &dmr_uncore_freerunning_ops,
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.event_descs = dmr_uncore_iio_freerunning_events,
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.format_group = &skx_uncore_iio_freerunning_format_group,
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};
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#define UNCORE_DMR_MMIO_EXTRA_UNCORES 1
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static struct intel_uncore_type *dmr_mmio_uncores[UNCORE_DMR_MMIO_EXTRA_UNCORES] = {
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&dmr_uncore_iio_free_running,
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};
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int dmr_uncore_pci_init(void)
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int dmr_uncore_pci_init(void)
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{
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{
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uncore_pci_uncores = uncore_get_uncores(UNCORE_ACCESS_PCI, 0, NULL,
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uncore_pci_uncores = uncore_get_uncores(UNCORE_ACCESS_PCI, 0, NULL,
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@ -6937,11 +7040,16 @@ int dmr_uncore_pci_init(void)
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dmr_uncores);
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dmr_uncores);
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return 0;
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return 0;
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}
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}
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void dmr_uncore_mmio_init(void)
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void dmr_uncore_mmio_init(void)
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{
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{
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uncore_mmio_uncores = uncore_get_uncores(UNCORE_ACCESS_MMIO, 0, NULL,
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uncore_mmio_uncores = uncore_get_uncores(UNCORE_ACCESS_MMIO,
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UNCORE_DMR_NUM_UNCORE_TYPES,
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UNCORE_DMR_MMIO_EXTRA_UNCORES,
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dmr_uncores);
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dmr_mmio_uncores,
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}
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UNCORE_DMR_NUM_UNCORE_TYPES,
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dmr_uncores);
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dmr_uncore_iio_free_running.num_boxes =
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uncore_type_max_boxes(uncore_mmio_uncores, UNCORE_DMR_ITC);
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}
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/* end of DMR uncore support */
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/* end of DMR uncore support */
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