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i2c-host for v7.1, part 2
- cx92755: convert I2C bindings to DT schema - mediatek: add optional bus power management during transfers - pxa: handle early bus busy condition -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQScDfrjQa34uOld1VLaeAVmJtMtbgUCaeQfzQAKCRDaeAVmJtMt bhZbAP4yxgj5FEkHaKYHEsUwXfh4zUEciWcXWaSrElrkn5/79AD/fy/zjO47zKEo KBf6uQurXv+RCT3uwDU5QowVoYuanwo= =5+1V -----END PGP SIGNATURE----- Merge tag 'i2c-host-7.1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow i2c-host for v7.1, part 2 - cx92755: convert I2C bindings to DT schema - mediatek: add optional bus power management during transfers - pxa: handle early bus busy condition
This commit is contained in:
Wolfram Sang
commit
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49
Documentation/devicetree/bindings/i2c/cnxt,cx92755-i2c.yaml
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49
Documentation/devicetree/bindings/i2c/cnxt,cx92755-i2c.yaml
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@ -0,0 +1,49 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/i2c/cnxt,cx92755-i2c.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Conexant Digicolor I2C controller
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allOf:
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- $ref: /schemas/i2c/i2c-controller.yaml#
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maintainers:
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- Baruch Siach <baruch@tkos.co.il>
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properties:
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compatible:
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const: cnxt,cx92755-i2c
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-frequency:
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default: 100000
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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i2c@f0000120 {
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compatible = "cnxt,cx92755-i2c";
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reg = <0xf0000120 0x10>;
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interrupts = <28>;
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clocks = <&main_clk>;
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clock-frequency = <100000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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@ -1,25 +0,0 @@
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Conexant Digicolor I2C controller
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Required properties:
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- compatible: must be "cnxt,cx92755-i2c"
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- reg: physical address and length of the device registers
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- interrupts: a single interrupt specifier
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- clocks: clock for the device
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- #address-cells: should be <1>
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- #size-cells: should be <0>
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Optional properties:
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- clock-frequency: the desired I2C bus clock frequency in Hz; in
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absence of this property the default value is used (100 kHz).
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Example:
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i2c: i2c@f0000120 {
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compatible = "cnxt,cx92755-i2c";
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reg = <0xf0000120 0x10>;
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interrupts = <28>;
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clocks = <&main_clk>;
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clock-frequency = <100000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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@ -21,6 +21,7 @@
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/scatterlist.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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@ -1244,9 +1245,15 @@ static int mtk_i2c_transfer(struct i2c_adapter *adap,
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bool write_then_read_en = false;
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struct mtk_i2c *i2c = i2c_get_adapdata(adap);
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if (i2c->adap.bus_regulator) {
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ret = regulator_enable(i2c->adap.bus_regulator);
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if (ret)
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return ret;
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}
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ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
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if (ret)
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return ret;
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goto err_regulator;
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i2c->auto_restart = i2c->dev_comp->auto_restart;
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@ -1301,6 +1308,10 @@ static int mtk_i2c_transfer(struct i2c_adapter *adap,
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err_exit:
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clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
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err_regulator:
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if (i2c->adap.bus_regulator)
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regulator_disable(i2c->adap.bus_regulator);
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return ret;
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}
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@ -71,6 +71,7 @@
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#define ISR_GCAD (1 << 8) /* general call address detected */
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#define ISR_SAD (1 << 9) /* slave address detected */
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#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
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#define ISR_A3700_EBB (1 << 11) /* early bus busy for armada 3700 */
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#define ILCR_SLV_SHIFT 0
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#define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
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@ -263,6 +264,7 @@ struct pxa_i2c {
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bool highmode_enter;
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u32 fm_mask;
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u32 hs_mask;
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u32 busy_mask;
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struct i2c_bus_recovery_info recovery;
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struct pinctrl *pinctrl;
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@ -430,7 +432,7 @@ static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
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while (1) {
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isr = readl(_ISR(i2c));
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if (!(isr & (ISR_IBB | ISR_UB)))
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if (!(isr & i2c->busy_mask))
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return 0;
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if (isr & ISR_SAD)
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@ -467,7 +469,7 @@ static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
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* quick check of the i2c lines themselves to ensure they've
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* gone high...
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*/
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if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 &&
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if ((readl(_ISR(i2c)) & i2c->busy_mask) == 0 &&
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readl(_IBMR(i2c)) == (IBMR_SCLS | IBMR_SDAS)) {
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if (i2c_debug > 0)
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dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
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@ -488,7 +490,7 @@ static int i2c_pxa_set_master(struct pxa_i2c *i2c)
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if (i2c_debug)
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dev_dbg(&i2c->adap.dev, "setting to bus master\n");
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if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
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if ((readl(_ISR(i2c)) & i2c->busy_mask) != 0) {
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dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
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if (!i2c_pxa_wait_master(i2c)) {
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dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
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@ -514,7 +516,7 @@ static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
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dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
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__func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
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if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
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if ((readl(_ISR(i2c)) & i2c->busy_mask) == 0 ||
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(readl(_ISR(i2c)) & ISR_SAD) != 0 ||
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(readl(_ICR(i2c)) & ICR_SCLE) == 0) {
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if (i2c_debug > 1)
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@ -1177,7 +1179,7 @@ static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
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/*
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* Wait for the bus to become free.
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*/
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while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB))
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while (timeout-- && readl(_ISR(i2c)) & i2c->busy_mask)
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udelay(1000);
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if (timeout < 0) {
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@ -1322,7 +1324,7 @@ static void i2c_pxa_unprepare_recovery(struct i2c_adapter *adap)
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* handing control of the bus back to avoid the bus changing state.
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*/
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isr = readl(_ISR(i2c));
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if (isr & (ISR_UB | ISR_IBB)) {
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if (isr & i2c->busy_mask) {
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dev_dbg(&i2c->adap.dev,
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"recovery: resetting controller, ISR=0x%08x\n", isr);
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i2c_pxa_do_reset(i2c);
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@ -1479,6 +1481,10 @@ static int i2c_pxa_probe(struct platform_device *dev)
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i2c->fm_mask = pxa_reg_layout[i2c_type].fm;
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i2c->hs_mask = pxa_reg_layout[i2c_type].hs;
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i2c->busy_mask = ISR_UB | ISR_IBB;
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if (i2c_type == REGS_A3700)
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i2c->busy_mask |= ISR_A3700_EBB;
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if (i2c_type != REGS_CE4100)
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i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
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