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drm/amd/pm: Add ppt1 support for smu_v13_0_12

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Add support to configure and retrieve ppt1 limit for smu_v13_0_12

v2: Add update_caps function and update ppt1 cap based on max ppt1
value, optimize the return values (Lijo)

v3: Add Null ptr check, return not supported in case of invalid
level/type (Lijo)

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Asad Kamal 2025-10-19 23:22:22 +08:00 committed by Alex Deucher
parent efa6bffae5
commit d88edb2460
4 changed files with 92 additions and 4 deletions
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4
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
View File

@ -286,7 +286,9 @@
__SMU_DUMMY_MAP(SetTimestamp), \
__SMU_DUMMY_MAP(GetTimestamp), \
__SMU_DUMMY_MAP(GetBadPageIpid), \
__SMU_DUMMY_MAP(EraseRasTable),
__SMU_DUMMY_MAP(EraseRasTable), \
__SMU_DUMMY_MAP(SetFastPptLimit), \
__SMU_DUMMY_MAP(GetFastPptLimit),
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(type) SMU_MSG_##type

8
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
View File

@ -148,6 +148,8 @@ const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(GetTimestamp, PPSMC_MSG_GetTimestamp, 0),
MSG_MAP(GetBadPageIpid, PPSMC_MSG_GetBadPageIpIdLoHi, 0),
MSG_MAP(EraseRasTable, PPSMC_MSG_EraseRasTable, 0),
MSG_MAP(SetFastPptLimit, PPSMC_MSG_SetFastPptLimit, 1),
MSG_MAP(GetFastPptLimit, PPSMC_MSG_GetFastPptLimit, 1),
};
int smu_v13_0_12_tables_init(struct smu_context *smu)
@ -354,6 +356,12 @@ int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu)
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(NPM_METRICS)))
pptable->MaxNodePowerLimit =
SMUQ10_ROUND(static_metrics->MaxNodePowerLimit);
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)) &&
static_metrics->PPT1Max) {
pptable->PPT1Max = static_metrics->PPT1Max;
pptable->PPT1Min = static_metrics->PPT1Min;
pptable->PPT1Default = static_metrics->PPT1Default;
}
smu_v13_0_12_init_xgmi_data(smu, static_metrics);
pptable->Init = true;
}

80
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
View File

@ -856,6 +856,17 @@ int smu_v13_0_6_get_static_metrics_table(struct smu_context *smu)
return 0;
}
static void smu_v13_0_6_update_caps(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct PPTable_t *pptable =
(struct PPTable_t *)smu_table->driver_pptable;
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)) &&
!pptable->PPT1Max)
smu_v13_0_6_cap_clear(smu, SMU_CAP(FAST_PPT));
}
static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
@ -872,8 +883,12 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
uint8_t max_width;
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) &&
smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
return smu_v13_0_12_setup_driver_pptable(smu);
smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) {
ret = smu_v13_0_12_setup_driver_pptable(smu);
if (ret)
return ret;
goto out;
}
/* Store one-time values in driver PPTable */
if (!pptable->Init) {
@ -953,7 +968,8 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
smu_v13_0_6_fill_static_metrics_table(smu, static_metrics);
}
}
out:
smu_v13_0_6_update_caps(smu);
return 0;
}
@ -1887,9 +1903,66 @@ static int smu_v13_0_6_set_power_limit(struct smu_context *smu,
enum smu_ppt_limit_type limit_type,
uint32_t limit)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct PPTable_t *pptable =
(struct PPTable_t *)smu_table->driver_pptable;
int ret;
if (limit_type == SMU_FAST_PPT_LIMIT) {
if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)))
return -EOPNOTSUPP;
if (limit > pptable->PPT1Max || limit < pptable->PPT1Min) {
dev_err(smu->adev->dev,
"New power limit (%d) should be between min %d max %d\n",
limit, pptable->PPT1Min, pptable->PPT1Max);
return -EINVAL;
}
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetFastPptLimit,
limit, NULL);
if (ret)
dev_err(smu->adev->dev, "Set fast PPT limit failed!\n");
return ret;
}
return smu_v13_0_set_power_limit(smu, limit_type, limit);
}
static int smu_v13_0_6_get_ppt_limit(struct smu_context *smu,
uint32_t *ppt_limit,
enum smu_ppt_limit_type type,
enum smu_ppt_limit_level level)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct PPTable_t *pptable =
(struct PPTable_t *)smu_table->driver_pptable;
int ret = 0;
if (type == SMU_FAST_PPT_LIMIT) {
if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)))
return -EOPNOTSUPP;
switch (level) {
case SMU_PPT_LIMIT_MAX:
*ppt_limit = pptable->PPT1Max;
break;
case SMU_PPT_LIMIT_CURRENT:
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPptLimit, ppt_limit);
if (ret)
dev_err(smu->adev->dev, "Get fast PPT limit failed!\n");
break;
case SMU_PPT_LIMIT_DEFAULT:
*ppt_limit = pptable->PPT1Default;
break;
case SMU_PPT_LIMIT_MIN:
*ppt_limit = pptable->PPT1Min;
break;
default:
return -EOPNOTSUPP;
}
return ret;
}
return -EOPNOTSUPP;
}
static int smu_v13_0_6_irq_process(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
@ -3959,6 +4032,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
.get_enabled_mask = smu_v13_0_6_get_enabled_mask,
.feature_is_enabled = smu_cmn_feature_is_enabled,
.set_power_limit = smu_v13_0_6_set_power_limit,
.get_ppt_limit = smu_v13_0_6_get_ppt_limit,
.set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
.register_irq_handler = smu_v13_0_6_register_irq_handler,
.enable_thermal_alert = smu_v13_0_enable_thermal_alert,

4
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
View File

@ -50,6 +50,9 @@ struct PPTable_t {
uint32_t MinLclkDpmRange;
uint64_t PublicSerialNumber_AID;
uint32_t MaxNodePowerLimit;
uint32_t PPT1Max;
uint32_t PPT1Min;
uint32_t PPT1Default;
bool Init;
};
@ -73,6 +76,7 @@ enum smu_v13_0_6_caps {
SMU_CAP(TEMP_METRICS),
SMU_CAP(NPM_METRICS),
SMU_CAP(RAS_EEPROM),
SMU_CAP(FAST_PPT),
SMU_CAP(ALL),
};