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dt-bindings: PCI: tegra264: Strictly distinguish C0 from C1-C5

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Instead of using the ECAM registers as the first entry, strictly make a
distinction between C0 and C1-C5. This is needed because otherwise the
unit address doesn't match the first "reg" entry. The ordering of these
nodes cannot be changed to follow the ECAM addresses because that would
put them outside of their "control bus" hierarchy since the ECAM address
space is a global one outside of any of the control busses.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260814-tegra264-pcie-v10-1-05d08c592b05@nvidia.com
This commit is contained in:
Thierry Reding 2026-08-14 17:38:55 +02:00 committed by Bjorn Helgaas
parent 071e245ab7
commit d86c91afe2
1 changed files with 50 additions and 25 deletions
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75
Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
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@ -10,32 +10,23 @@ maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: |
Of the six PCIe controllers found on Tegra264, one (C0) is used for the
internal GPU and the other five (C1-C5) are routed to connectors such as
PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1
through C5, but not for C0.
properties:
compatible:
const: nvidia,tegra264-pcie
reg:
description: |
Of the six PCIe controllers found on Tegra264, one (C0) is used for the
internal GPU and the other five (C1-C5) are routed to connectors such as
PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1
through C5, but not for C0.
minItems: 4
items:
- description: ECAM-compatible configuration space
- description: application layer registers
- description: transaction layer registers
- description: privileged transaction layer registers
- description: data link/physical layer registers (not available on C0)
maxItems: 5
reg-names:
minItems: 4
items:
- const: ecam
- const: xal
- const: xtl
- const: xtl-pri
- const: xpl
maxItems: 5
interrupts:
minItems: 1
@ -70,6 +61,40 @@ required:
allOf:
- $ref: /schemas/pci/pci-host-bridge.yaml#
- oneOf:
- description: C0 controller (no UPHY)
properties:
reg:
items:
- description: application layer registers
- description: transaction layer registers
- description: privileged transaction layer registers
- description: ECAM compatible configuration space
reg-names:
items:
- const: xal
- const: xtl
- const: xtl-pri
- const: ecam
- description: C1-C5 controllers (with UPHY)
properties:
reg:
items:
- description: application layer registers
- description: transaction layer registers
- description: privileged transaction layer registers
- description: data link/physical layer registers
- description: ECAM compatible configuration space
reg-names:
items:
- const: xal
- const: xtl
- const: xtl-pri
- const: xpl
- const: ecam
unevaluatedProperties: false
@ -81,11 +106,11 @@ examples:
pci@c000000 {
compatible = "nvidia,tegra264-pcie";
reg = <0xd0 0xb0000000 0x0 0x10000000>,
<0x00 0x0c000000 0x0 0x00004000>,
reg = <0x00 0x0c000000 0x0 0x00004000>,
<0x00 0x0c004000 0x0 0x00001000>,
<0x00 0x0c005000 0x0 0x00001000>;
reg-names = "ecam", "xal", "xtl", "xtl-pri";
<0x00 0x0c005000 0x0 0x00001000>,
<0xd0 0xb0000000 0x0 0x10000000>;
reg-names = "xal", "xtl", "xtl-pri", "ecam";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@ -118,12 +143,12 @@ examples:
pci@8400000 {
compatible = "nvidia,tegra264-pcie";
reg = <0xa8 0xb0000000 0x0 0x10000000>,
<0x00 0x08400000 0x0 0x00004000>,
reg = <0x00 0x08400000 0x0 0x00004000>,
<0x00 0x08404000 0x0 0x00001000>,
<0x00 0x08405000 0x0 0x00001000>,
<0x00 0x08410000 0x0 0x00010000>;
reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl";
<0x00 0x08410000 0x0 0x00010000>,
<0xa8 0xb0000000 0x0 0x10000000>;
reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";