github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-06-03 12:03:54 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

arm64: dts: imx8mn: Add display pipeline components

Browse Source 
Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Nano.
This makes the DSI display pipeline available on this SoC.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Marek Vasut 2023-04-05 18:52:13 +02:00 committed by Shawn Guo
parent c8c96afa6e
commit d825fb6455
1 changed files with 55 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -1057,6 +1057,61 @@ aips4: bus@32c00000 {
#size-cells = <1>; #size-cells = <1>;
ranges; ranges;
lcdif: lcdif@32e00000 {
compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif";
reg = <0x32e00000 0x10000>;
clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
<&clk IMX8MN_CLK_DISP_APB_ROOT>,
<&clk IMX8MN_CLK_DISP_AXI_ROOT>;
clock-names = "pix", "axi", "disp_axi";
assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
<&clk IMX8MN_CLK_DISP_AXI>,
<&clk IMX8MN_CLK_DISP_APB>;
assigned-clock-parents = <&clk IMX8MN_CLK_DISP_PIXEL>,
<&clk IMX8MN_SYS_PLL2_1000M>,
<&clk IMX8MN_SYS_PLL1_800M>;
assigned-clock-rates = <594000000>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>;
status = "disabled";
port {
lcdif_to_dsim: endpoint {
remote-endpoint = <&dsim_from_lcdif>;
};
};
};
mipi_dsi: dsi@32e10000 {
compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim";
reg = <0x32e10000 0x400>;
clocks = <&clk IMX8MN_CLK_DSI_CORE>,
<&clk IMX8MN_CLK_DSI_PHY_REF>;
clock-names = "bus_clk", "sclk_mipi";
assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
<&clk IMX8MN_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
<&clk IMX8MN_CLK_24M>;
assigned-clock-rates = <266000000>, <24000000>;
samsung,pll-clock-frequency = <24000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsim_from_lcdif: endpoint {
remote-endpoint = <&lcdif_to_dsim>;
};
};
};
};
disp_blk_ctrl: blk-ctrl@32e28000 { disp_blk_ctrl: blk-ctrl@32e28000 {
compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
reg = <0x32e28000 0x100>; reg = <0x32e28000 0x100>;