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media: tc358743: Add support for 972Mbit/s link freq
Adds register setups for running the CSI lanes at 972Mbit/s, which allows 1080P50 UYVY down 2 lanes. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
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@ -1993,6 +1993,7 @@ static int tc358743_probe_of(struct tc358743_state *state)
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/*
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* The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
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* The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
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* 972 Mbps allows 1080P50 UYVY over 2-lane.
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*/
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bps_pr_lane = 2 * endpoint.link_frequencies[0];
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if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
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@ -2006,23 +2007,42 @@ static int tc358743_probe_of(struct tc358743_state *state)
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state->pdata.refclk_hz * state->pdata.pll_prd;
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/*
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* FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
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* link frequency). In principle it should be possible to calculate
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* FIXME: These timings are from REF_02 for 594 or 972 Mbps per lane
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* (297 MHz or 486 MHz link frequency).
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* In principle it should be possible to calculate
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* them based on link frequency and resolution.
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*/
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if (bps_pr_lane != 594000000U)
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switch (bps_pr_lane) {
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default:
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dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
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state->pdata.lineinitcnt = 0xe80;
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state->pdata.lptxtimecnt = 0x003;
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/* tclk-preparecnt: 3, tclk-zerocnt: 20 */
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state->pdata.tclk_headercnt = 0x1403;
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state->pdata.tclk_trailcnt = 0x00;
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/* ths-preparecnt: 3, ths-zerocnt: 1 */
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state->pdata.ths_headercnt = 0x0103;
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state->pdata.twakeup = 0x4882;
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state->pdata.tclk_postcnt = 0x008;
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state->pdata.ths_trailcnt = 0x2;
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state->pdata.hstxvregcnt = 0;
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fallthrough;
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case 594000000U:
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state->pdata.lineinitcnt = 0xe80;
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state->pdata.lptxtimecnt = 0x003;
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/* tclk-preparecnt: 3, tclk-zerocnt: 20 */
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state->pdata.tclk_headercnt = 0x1403;
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state->pdata.tclk_trailcnt = 0x00;
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/* ths-preparecnt: 3, ths-zerocnt: 1 */
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state->pdata.ths_headercnt = 0x0103;
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state->pdata.twakeup = 0x4882;
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state->pdata.tclk_postcnt = 0x008;
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state->pdata.ths_trailcnt = 0x2;
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state->pdata.hstxvregcnt = 0;
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break;
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case 972000000U:
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state->pdata.lineinitcnt = 0x1b58;
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state->pdata.lptxtimecnt = 0x007;
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/* tclk-preparecnt: 6, tclk-zerocnt: 40 */
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state->pdata.tclk_headercnt = 0x2806;
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state->pdata.tclk_trailcnt = 0x00;
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/* ths-preparecnt: 6, ths-zerocnt: 8 */
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state->pdata.ths_headercnt = 0x0806;
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state->pdata.twakeup = 0x4268;
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state->pdata.tclk_postcnt = 0x008;
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state->pdata.ths_trailcnt = 0x5;
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state->pdata.hstxvregcnt = 0;
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break;
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}
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state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
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GPIOD_OUT_LOW);
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