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arm64: dts: qcom: monaco-monza-som: Fix the PCIe iommu-map entries

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The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe
iommu-map entries specify only one cell for the SID, omitting the SID
mask. This went unnoticed until the OF core started warning with commit
ccb2fd725d ("of: Respect #{iommu,msi}-cells in maps"):

  iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output

So fix the entries to match the provider's '#iommu-cells' property.

Fixes: 5238f4e716 ("arm64: dts: qcom: Add Monaco Monza SoM")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-16-83405d37ba41@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Manivannan Sadhasivam 2026-07-30 13:55:57 +02:00 committed by Bjorn Andersson
parent 2e455d9278
commit d7ae79013e
1 changed files with 8 additions and 8 deletions
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16
arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi
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@ -196,14 +196,14 @@ &iris {
/* PCIe0 Gen4 x2 */
&pcie0 {
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
<0x100 &pcie_smmu 0x0001 0x1>,
<0x200 &pcie_smmu 0x0007 0x1>,
<0x208 &pcie_smmu 0x0002 0x1>,
<0x210 &pcie_smmu 0x0003 0x1>,
<0x218 &pcie_smmu 0x0004 0x1>,
<0x300 &pcie_smmu 0x0005 0x1>,
<0x400 &pcie_smmu 0x0006 0x1>;
iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>,
<0x100 &pcie_smmu 0x0001 0x0 0x1>,
<0x200 &pcie_smmu 0x0007 0x0 0x1>,
<0x208 &pcie_smmu 0x0002 0x0 0x1>,
<0x210 &pcie_smmu 0x0003 0x0 0x1>,
<0x218 &pcie_smmu 0x0004 0x0 0x1>,
<0x300 &pcie_smmu 0x0005 0x0 0x1>,
<0x400 &pcie_smmu 0x0006 0x0 0x1>;
status = "okay";
};