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drm/amd/display: Fix Silence Conversion Warnings in Dmub

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Fix Conversion that might result in a loss of data  warnings in dmub/src/:

- dmub_dcn20/31/32/35/42/60/401.c: Add ASSERT(value <= 0xFF) and
  explicit (uint8_t) cast when storing REG_GET results into uint8_t
  debug struct fields. Add != 0 for bool assignments from uint32_t
  bitfield reads.
- dmub_reg.c: Cast va_arg shift value to uint8_t with ASSERT guard
  before passing to set_reg_field_value_masks().
- dmub_srv.c: Widen num_pending to uint64_t to match uint64_t
  arithmetic; use != 0 for bool assignments from unsigned expressions.

No functional change intended.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Gaghik Khachatrian 2026-03-16 16:05:31 -04:00 committed by Alex Deucher
parent 4c3aeb11d5
commit d77ff7331f
8 changed files with 82 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
View File

@ -460,20 +460,26 @@ void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub)
dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
dmub->debug.is_dmcub_enabled = is_dmub_enabled;
ASSERT(is_dmub_enabled <= 0xFF);
dmub->debug.is_dmcub_enabled = (uint8_t)is_dmub_enabled;
REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset);
dmub->debug.is_dmcub_soft_reset = is_soft_reset;
ASSERT(is_soft_reset <= 0xFF);
dmub->debug.is_dmcub_soft_reset = (uint8_t)is_soft_reset;
REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
dmub->debug.is_dmcub_secure_reset = is_sec_reset;
ASSERT(is_sec_reset <= 0xFF);
dmub->debug.is_dmcub_secure_reset = (uint8_t)is_sec_reset;
REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
dmub->debug.is_traceport_en = is_traceport_enabled;
ASSERT(is_traceport_enabled <= 0xFF);
dmub->debug.is_traceport_en = (uint8_t)is_traceport_enabled;
REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
dmub->debug.is_cw0_enabled = is_cw0_enabled;
ASSERT(is_cw0_enabled <= 0xFF);
dmub->debug.is_cw0_enabled = (uint8_t)is_cw0_enabled;
REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
dmub->debug.is_cw6_enabled = is_cw6_enabled;
ASSERT(is_cw6_enabled <= 0xFF);
dmub->debug.is_cw6_enabled = (uint8_t)is_cw6_enabled;
}

21
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
View File

@ -466,25 +466,32 @@ void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub)
dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
dmub->debug.is_dmcub_enabled = is_dmub_enabled;
ASSERT(is_dmub_enabled <= 0xFF);
dmub->debug.is_dmcub_enabled = (uint8_t)is_dmub_enabled;
REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait);
dmub->debug.is_pwait = is_pwait;
ASSERT(is_pwait <= 0xFF);
dmub->debug.is_pwait = (uint8_t)is_pwait;
REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
dmub->debug.is_dmcub_soft_reset = is_soft_reset;
ASSERT(is_soft_reset <= 0xFF);
dmub->debug.is_dmcub_soft_reset = (uint8_t)is_soft_reset;
REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
dmub->debug.is_dmcub_secure_reset = is_sec_reset;
ASSERT(is_sec_reset <= 0xFF);
dmub->debug.is_dmcub_secure_reset = (uint8_t)is_sec_reset;
REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
dmub->debug.is_traceport_en = is_traceport_enabled;
ASSERT(is_traceport_enabled <= 0xFF);
dmub->debug.is_traceport_en = (uint8_t)is_traceport_enabled;
REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
dmub->debug.is_cw0_enabled = is_cw0_enabled;
ASSERT(is_cw0_enabled <= 0xFF);
dmub->debug.is_cw0_enabled = (uint8_t)is_cw0_enabled;
REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
dmub->debug.is_cw6_enabled = is_cw6_enabled;
ASSERT(is_cw6_enabled <= 0xFF);
dmub->debug.is_cw6_enabled = (uint8_t)is_cw6_enabled;
}
bool dmub_dcn31_should_detect(struct dmub_srv *dmub)

15
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
View File

@ -486,19 +486,24 @@ void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub)
dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
dmub->debug.is_dmcub_enabled = is_dmub_enabled;
ASSERT(is_dmub_enabled <= 0xFF);
dmub->debug.is_dmcub_enabled = (uint8_t)is_dmub_enabled;
REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait);
dmub->debug.is_pwait = is_pwait;
ASSERT(is_pwait <= 0xFF);
dmub->debug.is_pwait = (uint8_t)is_pwait;
REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
dmub->debug.is_dmcub_soft_reset = is_soft_reset;
ASSERT(is_soft_reset <= 0xFF);
dmub->debug.is_dmcub_soft_reset = (uint8_t)is_soft_reset;
REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
dmub->debug.is_traceport_en = is_traceport_enabled;
ASSERT(is_traceport_enabled <= 0xFF);
dmub->debug.is_traceport_en = (uint8_t)is_traceport_enabled;
REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
dmub->debug.is_cw6_enabled = is_cw6_enabled;
ASSERT(is_cw6_enabled <= 0xFF);
dmub->debug.is_cw6_enabled = (uint8_t)is_cw6_enabled;
dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
}

17
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
View File

@ -402,7 +402,7 @@ void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu
union dmub_fw_boot_options boot_options = {0};
if (!dmub->dpia_supported) {
dmub->dpia_supported = dmub_dcn35_get_fw_boot_option(dmub).bits.enable_dpia;
dmub->dpia_supported = dmub_dcn35_get_fw_boot_option(dmub).bits.enable_dpia != 0;
}
boot_options.bits.z10_disable = params->disable_z10;
@ -508,19 +508,24 @@ void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub)
dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
dmub->debug.is_dmcub_enabled = is_dmub_enabled;
ASSERT(is_dmub_enabled <= 0xFF);
dmub->debug.is_dmcub_enabled = (uint8_t)is_dmub_enabled;
REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait);
dmub->debug.is_pwait = is_pwait;
ASSERT(is_pwait <= 0xFF);
dmub->debug.is_pwait = (uint8_t)is_pwait;
REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
dmub->debug.is_dmcub_soft_reset = is_soft_reset;
ASSERT(is_soft_reset <= 0xFF);
dmub->debug.is_dmcub_soft_reset = (uint8_t)is_soft_reset;
REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
dmub->debug.is_traceport_en = is_traceport_enabled;
ASSERT(is_traceport_enabled <= 0xFF);
dmub->debug.is_traceport_en = (uint8_t)is_traceport_enabled;
REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
dmub->debug.is_cw6_enabled = is_cw6_enabled;
ASSERT(is_cw6_enabled <= 0xFF);
dmub->debug.is_cw6_enabled = (uint8_t)is_cw6_enabled;
dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
}

21
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
View File

@ -473,25 +473,32 @@ void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub)
dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
dmub->debug.is_dmcub_enabled = is_dmub_enabled;
ASSERT(is_dmub_enabled <= 0xFF);
dmub->debug.is_dmcub_enabled = (uint8_t)is_dmub_enabled;
REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait);
dmub->debug.is_pwait = is_pwait;
ASSERT(is_pwait <= 0xFF);
dmub->debug.is_pwait = (uint8_t)is_pwait;
REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
dmub->debug.is_dmcub_soft_reset = is_soft_reset;
ASSERT(is_soft_reset <= 0xFF);
dmub->debug.is_dmcub_soft_reset = (uint8_t)is_soft_reset;
REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
dmub->debug.is_dmcub_secure_reset = is_sec_reset;
ASSERT(is_sec_reset <= 0xFF);
dmub->debug.is_dmcub_secure_reset = (uint8_t)is_sec_reset;
REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
dmub->debug.is_traceport_en = is_traceport_enabled;
ASSERT(is_traceport_enabled <= 0xFF);
dmub->debug.is_traceport_en = (uint8_t)is_traceport_enabled;
REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
dmub->debug.is_cw0_enabled = is_cw0_enabled;
ASSERT(is_cw0_enabled <= 0xFF);
dmub->debug.is_cw0_enabled = (uint8_t)is_cw0_enabled;
REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
dmub->debug.is_cw6_enabled = is_cw6_enabled;
ASSERT(is_cw6_enabled <= 0xFF);
dmub->debug.is_cw6_enabled = (uint8_t)is_cw6_enabled;
dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
}

23
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
View File

@ -41,7 +41,7 @@ void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu
union dmub_fw_boot_options boot_options = {0};
if (!dmub->dpia_supported) {
dmub->dpia_supported = dmub_dcn42_get_fw_boot_option(dmub).bits.enable_dpia;
dmub->dpia_supported = dmub_dcn42_get_fw_boot_option(dmub).bits.enable_dpia != 0;
}
boot_options.bits.z10_disable = params->disable_z10;
@ -676,25 +676,32 @@ void dmub_dcn42_get_diagnostic_data(struct dmub_srv *dmub)
dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
dmub->debug.is_dmcub_enabled = is_dmub_enabled;
ASSERT(is_dmub_enabled <= 0xFF);
dmub->debug.is_dmcub_enabled = (uint8_t)is_dmub_enabled;
REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait);
dmub->debug.is_pwait = is_pwait;
ASSERT(is_pwait <= 0xFF);
dmub->debug.is_pwait = (uint8_t)is_pwait;
REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
dmub->debug.is_dmcub_soft_reset = is_soft_reset;
ASSERT(is_soft_reset <= 0xFF);
dmub->debug.is_dmcub_soft_reset = (uint8_t)is_soft_reset;
REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
dmub->debug.is_dmcub_secure_reset = is_sec_reset;
ASSERT(is_sec_reset <= 0xFF);
dmub->debug.is_dmcub_secure_reset = (uint8_t)is_sec_reset;
REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
dmub->debug.is_traceport_en = is_traceport_enabled;
ASSERT(is_traceport_enabled <= 0xFF);
dmub->debug.is_traceport_en = (uint8_t)is_traceport_enabled;
REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
dmub->debug.is_cw0_enabled = is_cw0_enabled;
ASSERT(is_cw0_enabled <= 0xFF);
dmub->debug.is_cw0_enabled = (uint8_t)is_cw0_enabled;
REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
dmub->debug.is_cw6_enabled = is_cw6_enabled;
ASSERT(is_cw6_enabled <= 0xFF);
dmub->debug.is_cw6_enabled = (uint8_t)is_cw6_enabled;
dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
}

3
drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c
View File

@ -57,8 +57,9 @@ static void set_reg_field_values(struct dmub_reg_value_masks *field_value_mask,
mask = va_arg(ap, uint32_t);
field_value = va_arg(ap, uint32_t);
ASSERT(shift <= 0xFF);
set_reg_field_value_masks(field_value_mask, field_value, mask,
shift);
(uint8_t)shift);
i++;
}
}

8
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
View File

@ -1034,8 +1034,8 @@ enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
static void dmub_srv_update_reg_inbox0_status(struct dmub_srv *dmub)
{
if (dmub->reg_inbox0.is_pending) {
dmub->reg_inbox0.is_pending = dmub->hw_funcs.read_reg_inbox0_rsp_int_status &&
!dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub);
dmub->reg_inbox0.is_pending = (dmub->hw_funcs.read_reg_inbox0_rsp_int_status &&
!dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub)) != 0;
if (!dmub->reg_inbox0.is_pending) {
/* ack the rsp interrupt */
@ -1320,7 +1320,7 @@ void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_t
enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd)
{
uint32_t num_pending = 0;
uint64_t num_pending = 0;
if (!dmub->hw_init)
return DMUB_STATUS_INVALID;
@ -1348,7 +1348,7 @@ enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_c
dmub->reg_inbox0.num_submitted++;
dmub->reg_inbox0.is_pending = true;
dmub->reg_inbox0.is_multi_pending = cmd->cmd_common.header.multi_cmd_pending;
dmub->reg_inbox0.is_multi_pending = cmd->cmd_common.header.multi_cmd_pending != 0;
return DMUB_STATUS_OK;
}