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drm/rockchip: dsi: make rk356x series drive pixdata on posedge

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fix the dclk polarity in the driver to avoid incorrect
configuration, even if we can configure through attribute
pixelclk-active in dts.

Change-Id: Ie3861206d2f6312ef252df87ecb49dd7d5f0ba9b
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
This commit is contained in:
Guochun Huang 2021-02-18 09:27:17 +08:00 committed by Tao Huang
parent a695fea288
commit d75f6df07e
1 changed files with 25 additions and 0 deletions
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25
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
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@ -205,6 +205,13 @@ enum {
BIASEXTR_127_7,
};
enum soc_type {
PX30,
RK3288,
RK3399,
RK3568,
};
struct rockchip_dw_dsi_chip_data {
u32 reg;
@ -220,6 +227,7 @@ struct rockchip_dw_dsi_chip_data {
u32 lanecfg2_grf_reg;
u32 lanecfg2;
enum soc_type soc_type;
unsigned int flags;
unsigned int max_data_lanes;
};
@ -754,6 +762,12 @@ dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
else
s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
/* rk356x series drive mipi pixdata on posedge */
if (dsi->cdata->soc_type == RK3568) {
s->bus_flags &= ~DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE;
s->bus_flags |= DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE;
}
s->output_type = DRM_MODE_CONNECTOR_DSI;
s->color_space = V4L2_COLORSPACE_DEFAULT;
s->output_if = dsi->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0;
@ -762,6 +776,10 @@ dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
s->output_if |= VOP_OUTPUT_IF_MIPI1;
}
/* dual link dsi for rk3399 */
if (dsi->id && dsi->cdata->soc_type == RK3399)
s->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP;
return 0;
}
@ -1197,6 +1215,7 @@ static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
PX30_DSI_FORCETXSTOPMODE),
.max_data_lanes = 4,
.soc_type = PX30,
},
{ /* sentinel */ }
};
@ -1209,6 +1228,7 @@ static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
.lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
.max_data_lanes = 4,
.soc_type = RK3288,
},
{
.reg = 0xff964000,
@ -1217,6 +1237,7 @@ static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
.lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
.max_data_lanes = 4,
.soc_type = RK3288,
},
{ /* sentinel */ }
};
@ -1237,6 +1258,7 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
.flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
.max_data_lanes = 4,
.soc_type = RK3399,
},
{
.reg = 0xff968000,
@ -1263,6 +1285,7 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
.flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
.max_data_lanes = 4,
.soc_type = RK3399,
},
{ /* sentinel */ }
};
@ -1278,6 +1301,7 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {
.flags = DW_MIPI_NEEDS_HCLK,
.max_data_lanes = 4,
.soc_type = RK3568,
},
{
.reg = 0xfe070000,
@ -1289,6 +1313,7 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {
.flags = DW_MIPI_NEEDS_HCLK,
.max_data_lanes = 4,
.soc_type = RK3568,
},
{ /* sentinel */ }
};