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drm/rockchip: vop: Consistently use rk3399 registers consts

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As rk3399 has its own registers definitions, update related structs to
use them.
There are no changes in behaviour as updated constants values are the
 for rk3288/rk3368/rk3399 chips.

Signed-off-by: Konstantin Shabanov <mail@etehtsea.me>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250403064740.4016-1-mail@etehtsea.me
This commit is contained in:
Konstantin Shabanov 2025-04-03 06:47:39 +00:00 committed by Heiko Stuebner
parent 64e6121dc1
commit d74cc229cf
1 changed files with 47 additions and 47 deletions
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94
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
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@ -906,21 +906,21 @@ static const struct vop_data rk3366_vop = {
static const struct vop_output rk3399_output = {
.dp_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 19),
.rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19),
.hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23),
.edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27),
.mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31),
.rgb_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 19),
.hdmi_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 23),
.edp_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 27),
.mipi_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 31),
.dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 16),
.rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16),
.hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20),
.edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24),
.mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28),
.rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 16),
.hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 20),
.edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 24),
.mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 28),
.dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
.mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
.mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3),
.rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
.hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13),
.edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14),
.mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15),
.mipi_dual_channel_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 3),
};
static const struct vop_common rk3399_common = {
@ -975,23 +975,23 @@ static const struct vop_win_phy rk3399_win0_data = {
.data_formats = formats_win_full_10,
.nformats = ARRAY_SIZE(formats_win_full_10),
.format_modifiers = format_modifiers_win_full_afbc,
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
.x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
.y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22),
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
.channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
.enable = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3399_WIN0_CTRL0, 0x7, 1),
.fmt_10 = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 4),
.rb_swap = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 12),
.uv_swap = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 15),
.x_mir_en = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 21),
.y_mir_en = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 22),
.act_info = VOP_REG(RK3399_WIN0_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3399_WIN0_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3399_WIN0_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3399_WIN0_YRGB_MST, 0xffffffff, 0),
.uv_mst = VOP_REG(RK3399_WIN0_CBR_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3399_WIN0_VIR, 0x3fff, 0),
.uv_vir = VOP_REG(RK3399_WIN0_VIR, 0x3fff, 16),
.src_alpha_ctl = VOP_REG(RK3399_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
.dst_alpha_ctl = VOP_REG(RK3399_WIN0_DST_ALPHA_CTRL, 0xff, 0),
.channel = VOP_REG(RK3399_WIN0_CTRL2, 0xff, 0),
};
static const struct vop_win_phy rk3399_win1_data = {
@ -999,23 +999,23 @@ static const struct vop_win_phy rk3399_win1_data = {
.data_formats = formats_win_full_10,
.nformats = ARRAY_SIZE(formats_win_full_10),
.format_modifiers = format_modifiers_win_full,
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
.x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
.y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22),
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
.channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
.enable = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3399_WIN0_CTRL0, 0x7, 1),
.fmt_10 = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 4),
.rb_swap = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 12),
.uv_swap = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 15),
.x_mir_en = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 21),
.y_mir_en = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 22),
.act_info = VOP_REG(RK3399_WIN0_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3399_WIN0_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3399_WIN0_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3399_WIN0_YRGB_MST, 0xffffffff, 0),
.uv_mst = VOP_REG(RK3399_WIN0_CBR_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3399_WIN0_VIR, 0x3fff, 0),
.uv_vir = VOP_REG(RK3399_WIN0_VIR, 0x3fff, 16),
.src_alpha_ctl = VOP_REG(RK3399_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
.dst_alpha_ctl = VOP_REG(RK3399_WIN0_DST_ALPHA_CTRL, 0xff, 0),
.channel = VOP_REG(RK3399_WIN0_CTRL2, 0xff, 0),
};
/*