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net: phy: dp83867: Program TX FIFO for all interfaces

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All supported interfaces use the TX FIFO register at least some of the
time, so there's no point in checking the interface. Retain the check
for the RX FIFO level since it is only used by SGMII.

Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Link: https://patch.msgid.link/20260129171205.3868605-2-sean.anderson@linux.dev
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Sean Anderson 2026-01-29 12:12:04 -05:00 committed by Jakub Kicinski
parent 82f35bec11
commit d700b2a440
1 changed files with 14 additions and 17 deletions
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31
drivers/net/phy/dp83867.c
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@ -744,27 +744,24 @@ static int dp83867_config_init(struct phy_device *phydev)
*/
phy_disable_eee(phydev);
if (phy_interface_is_rgmii(phydev) ||
phydev->interface == PHY_INTERFACE_MODE_SGMII) {
val = phy_read(phydev, MII_DP83867_PHYCTRL);
if (val < 0)
return val;
val = phy_read(phydev, MII_DP83867_PHYCTRL);
if (val < 0)
return val;
val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
val |= (dp83867->tx_fifo_depth <<
DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
val |= (dp83867->tx_fifo_depth <<
DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
val |= (dp83867->rx_fifo_depth <<
DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
}
ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
if (ret)
return ret;
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
val |= (dp83867->rx_fifo_depth <<
DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
}
ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
if (ret)
return ret;
if (phy_interface_is_rgmii(phydev)) {
val = phy_read(phydev, MII_DP83867_PHYCTRL);
if (val < 0)