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iio: adc: mt6323-auxadc: add mt6323 PMIC AUXADC driver
The mt6323 AUXADC is a 15-bit ADC used for system monitoring. This driver provides support for reading various channels including battery and charger voltages, battery and chip temperature, current sensing and accessory detection. Add a driver for the AUXADC found in the MediaTek mt6323 PMIC. Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation) Signed-off-by: Roman Vivchar <rva333@protonmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Reviewed-by: David Lechner <dlechner@baylibre.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This commit is contained in:
Roman Vivchar
Jonathan Cameron
parent
348ff65577
commit
d6c384c326
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@ -16568,6 +16568,7 @@ MEDIATEK MT6323 PMIC AUXADC DRIVER
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M: Roman Vivchar <rva333@protonmail.com>
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L: linux-iio@vger.kernel.org
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S: Maintained
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F: drivers/iio/adc/mt6323-auxadc.c
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F: include/dt-bindings/iio/adc/mediatek,mt6323-auxadc.h
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MEDIATEK MT6735 CLOCK & RESET DRIVERS
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@ -1163,6 +1163,17 @@ config MCP3911
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This driver can also be built as a module. If so, the module will be
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called mcp3911.
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config MEDIATEK_MT6323_AUXADC
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tristate "MediaTek MT6323 PMIC AUXADC driver"
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depends on MFD_MT6397
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help
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Say yes here to enable support for MediaTek MT6323 PMIC Auxiliary ADC.
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This driver provides multiple channels for system monitoring,
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such as battery voltage, PMIC temperature, and others.
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This driver can also be built as a module. If so, the module will be
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called mt6323-auxadc.
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config MEDIATEK_MT6359_AUXADC
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tristate "MediaTek MT6359 PMIC AUXADC driver"
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depends on MFD_MT6397
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@ -100,6 +100,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
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obj-$(CONFIG_MCP3422) += mcp3422.o
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obj-$(CONFIG_MCP3564) += mcp3564.o
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obj-$(CONFIG_MCP3911) += mcp3911.o
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obj-$(CONFIG_MEDIATEK_MT6323_AUXADC) += mt6323-auxadc.o
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obj-$(CONFIG_MEDIATEK_MT6359_AUXADC) += mt6359-auxadc.o
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obj-$(CONFIG_MEDIATEK_MT6360_ADC) += mt6360-adc.o
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obj-$(CONFIG_MEDIATEK_MT6370_ADC) += mt6370-adc.o
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314
drivers/iio/adc/mt6323-auxadc.c
Normal file
314
drivers/iio/adc/mt6323-auxadc.c
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@ -0,0 +1,314 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2026 Roman Vivchar <rva333@protonmail.com>
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*
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* Based on drivers/iio/adc/mt6359-auxadc.c
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*/
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#include <linux/array_size.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/cleanup.h>
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#include <linux/delay.h>
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#include <linux/iio/iio.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/stringify.h>
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#include <linux/time.h>
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#include <linux/types.h>
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#include <linux/mfd/mt6323/registers.h>
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#include <dt-bindings/iio/adc/mediatek,mt6323-auxadc.h>
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#define AUXADC_STRUP_CON10_RSTB_SEL BIT(7)
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#define AUXADC_STRUP_CON10_RSTB_SW BIT(5)
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#define AUXADC_TOP_CKPDN2_CTL_CK BIT(5)
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#define AUXADC_TRIM_CH2_MASK GENMASK(11, 10)
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#define AUXADC_TRIM_CH4_MASK GENMASK(9, 8)
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#define AUXADC_TRIM_CH5_MASK GENMASK(5, 4)
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#define AUXADC_TRIM_CH6_MASK GENMASK(3, 2)
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#define AUXADC_CON27_VREF18_ENB_MD BIT(15)
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#define AUXADC_CON27_MD_STATUS BIT(0)
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#define AUXADC_CON19_GPS_STATUS BIT(1)
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#define AUXADC_CON26_VREF18_SELB BIT(1)
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#define AUXADC_CON26_DECI_GDLY_SEL BIT(0)
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#define AUXADC_CON11_VBUF_EN BIT(4)
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#define AUXADC_CON19_DECI_GDLY_MASK GENMASK(15, 14)
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#define AUXADC_ADC19_BUSY_MASK GENMASK(15, 1)
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#define AUXADC_READY_MASK BIT(15)
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#define AUXADC_DATA_MASK GENMASK(14, 0)
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#define AUXADC_CON9_OSR_MASK GENMASK(12, 10)
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#define AUXADC_DEFAULT_OSR 3
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#define MTK_PMIC_IIO_CHAN(_name, _chan, _addr) \
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{ \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = _chan, \
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.address = _addr, \
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.datasheet_name = __stringify(_name), \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE), \
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}
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/*
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* AUXADC reports everything in mV, including temperature and
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* current channels. Channel macros are mapped such that their
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* ID matches their respective hardware bit position in CON22.
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*/
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static const struct iio_chan_spec mt6323_auxadc_channels[] = {
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MTK_PMIC_IIO_CHAN(baton2, MT6323_AUXADC_BATON2, MT6323_AUXADC_ADC6),
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MTK_PMIC_IIO_CHAN(ch6, MT6323_AUXADC_CH6, MT6323_AUXADC_ADC11),
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MTK_PMIC_IIO_CHAN(bat_temp, MT6323_AUXADC_BAT_TEMP, MT6323_AUXADC_ADC5),
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MTK_PMIC_IIO_CHAN(chip_temp, MT6323_AUXADC_CHIP_TEMP, MT6323_AUXADC_ADC4),
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MTK_PMIC_IIO_CHAN(vcdt, MT6323_AUXADC_VCDT, MT6323_AUXADC_ADC2),
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MTK_PMIC_IIO_CHAN(baton1, MT6323_AUXADC_BATON1, MT6323_AUXADC_ADC3),
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MTK_PMIC_IIO_CHAN(isense, MT6323_AUXADC_ISENSE, MT6323_AUXADC_ADC1),
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MTK_PMIC_IIO_CHAN(batsns, MT6323_AUXADC_BATSNS, MT6323_AUXADC_ADC0),
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MTK_PMIC_IIO_CHAN(accdet, MT6323_AUXADC_ACCDET, MT6323_AUXADC_ADC7),
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};
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/*
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* The MediaTek MT6323 (as well as a lot of other PMICs) has the following hierarchy:
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* PMIC AUXADC <- PMIC MFD <- SoC PWRAP (wrapper for PWRAP FSM)
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*
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* Therefore, PWRAP regmap should be obtained using dev->parent->parent.
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*/
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struct mt6323_auxadc {
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struct regmap *regmap;
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/* AUXADC doesn't support reading multiple channels simultaneously. */
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struct mutex lock;
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};
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static int mt6323_auxadc_prepare_channel(struct mt6323_auxadc *auxadc)
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{
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struct regmap *map = auxadc->regmap;
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u32 val;
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int ret;
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ret = regmap_read(map, MT6323_AUXADC_CON19, &val);
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if (ret)
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return ret;
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/* The ADC is idle. */
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if (!(val & AUXADC_CON19_DECI_GDLY_MASK))
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return 0;
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ret = regmap_read_poll_timeout(map, MT6323_AUXADC_ADC19,
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val, !(val & AUXADC_ADC19_BUSY_MASK),
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10, 500);
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if (ret)
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return ret;
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return regmap_clear_bits(map, MT6323_AUXADC_CON19,
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AUXADC_CON19_DECI_GDLY_MASK);
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}
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static int mt6323_auxadc_request(struct mt6323_auxadc *auxadc,
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unsigned long channel)
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{
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struct regmap *map = auxadc->regmap;
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int ret;
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ret = regmap_set_bits(map, MT6323_AUXADC_CON11, AUXADC_CON11_VBUF_EN);
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if (ret)
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return ret;
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return regmap_set_bits(map, MT6323_AUXADC_CON22, BIT(channel));
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}
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static int mt6323_auxadc_release(struct mt6323_auxadc *auxadc,
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unsigned long channel)
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{
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struct regmap *map = auxadc->regmap;
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int ret;
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ret = regmap_clear_bits(map, MT6323_AUXADC_CON22, BIT(channel));
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if (ret)
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return ret;
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return regmap_clear_bits(map, MT6323_AUXADC_CON11, AUXADC_CON11_VBUF_EN);
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}
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static int mt6323_auxadc_read(struct mt6323_auxadc *auxadc,
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const struct iio_chan_spec *chan, int *out)
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{
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struct regmap *map = auxadc->regmap;
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u32 val;
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int ret;
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ret = regmap_read_poll_timeout(map, chan->address,
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val, (val & AUXADC_READY_MASK),
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1 * USEC_PER_MSEC, 100 * USEC_PER_MSEC);
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if (ret)
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return ret;
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*out = FIELD_GET(AUXADC_DATA_MASK, val);
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return 0;
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}
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static int mt6323_auxadc_read_raw(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan,
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int *val, int *val2, long mask)
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{
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struct mt6323_auxadc *auxadc = iio_priv(indio_dev);
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int ret, mult;
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switch (mask) {
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case IIO_CHAN_INFO_SCALE:
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if (chan->channel == MT6323_AUXADC_ISENSE ||
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chan->channel == MT6323_AUXADC_BATSNS)
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mult = 4;
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else
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mult = 1;
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/* 1800mV full range with 15-bit resolution. */
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*val = mult * 1800;
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*val2 = 15;
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return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_CHAN_INFO_RAW: {
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guard(mutex)(&auxadc->lock);
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ret = mt6323_auxadc_prepare_channel(auxadc);
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if (ret)
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return ret;
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ret = mt6323_auxadc_request(auxadc, chan->channel);
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if (ret)
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return ret;
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/* Hardware limitation: the AUXADC needs a delay to become ready. */
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fsleep(300);
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ret = mt6323_auxadc_read(auxadc, chan, val);
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if (mt6323_auxadc_release(auxadc, chan->channel))
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dev_err(&indio_dev->dev,
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"failed to release channel %d\n", chan->channel);
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if (ret)
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return ret;
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return IIO_VAL_INT;
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}
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default:
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return -EINVAL;
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}
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}
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static int mt6323_auxadc_init(struct mt6323_auxadc *auxadc)
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{
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struct regmap *map = auxadc->regmap;
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int ret;
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ret = regmap_set_bits(map, MT6323_STRUP_CON10,
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AUXADC_STRUP_CON10_RSTB_SW |
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AUXADC_STRUP_CON10_RSTB_SEL);
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if (ret)
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return ret;
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ret = regmap_set_bits(map, MT6323_TOP_CKPDN2, AUXADC_TOP_CKPDN2_CTL_CK);
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if (ret)
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return ret;
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ret = regmap_update_bits(map, MT6323_AUXADC_CON10,
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AUXADC_TRIM_CH2_MASK | AUXADC_TRIM_CH4_MASK |
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AUXADC_TRIM_CH5_MASK | AUXADC_TRIM_CH6_MASK,
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FIELD_PREP(AUXADC_TRIM_CH2_MASK, 1) |
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FIELD_PREP(AUXADC_TRIM_CH4_MASK, 1) |
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FIELD_PREP(AUXADC_TRIM_CH5_MASK, 1) |
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FIELD_PREP(AUXADC_TRIM_CH6_MASK, 1));
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if (ret)
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return ret;
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ret = regmap_set_bits(map, MT6323_AUXADC_CON27,
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AUXADC_CON27_VREF18_ENB_MD |
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AUXADC_CON27_MD_STATUS);
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if (ret)
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return ret;
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ret = regmap_set_bits(map, MT6323_AUXADC_CON19, AUXADC_CON19_GPS_STATUS);
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if (ret)
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return ret;
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ret = regmap_set_bits(map, MT6323_AUXADC_CON26,
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AUXADC_CON26_VREF18_SELB |
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AUXADC_CON26_DECI_GDLY_SEL);
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if (ret)
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return ret;
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return regmap_update_bits(map, MT6323_AUXADC_CON9, AUXADC_CON9_OSR_MASK,
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FIELD_PREP(AUXADC_CON9_OSR_MASK, AUXADC_DEFAULT_OSR));
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}
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static const struct iio_info mt6323_auxadc_iio_info = {
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.read_raw = mt6323_auxadc_read_raw,
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};
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static int mt6323_auxadc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mt6323_auxadc *auxadc;
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struct regmap *regmap;
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struct iio_dev *iio;
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int ret;
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regmap = dev_get_regmap(dev->parent->parent, NULL);
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if (!regmap)
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return dev_err_probe(dev, -ENODEV, "failed to get regmap\n");
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iio = devm_iio_device_alloc(dev, sizeof(*auxadc));
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if (!iio)
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return -ENOMEM;
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auxadc = iio_priv(iio);
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auxadc->regmap = regmap;
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ret = devm_mutex_init(dev, &auxadc->lock);
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if (ret)
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return ret;
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ret = mt6323_auxadc_init(auxadc);
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if (ret)
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return dev_err_probe(dev, ret, "failed to initialize auxadc\n");
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iio->name = "mt6323-auxadc";
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iio->info = &mt6323_auxadc_iio_info;
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iio->modes = INDIO_DIRECT_MODE;
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iio->channels = mt6323_auxadc_channels;
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iio->num_channels = ARRAY_SIZE(mt6323_auxadc_channels);
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return devm_iio_device_register(dev, iio);
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}
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static const struct of_device_id mt6323_auxadc_of_match[] = {
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{ .compatible = "mediatek,mt6323-auxadc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, mt6323_auxadc_of_match);
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static struct platform_driver mt6323_auxadc_driver = {
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.driver = {
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.name = "mt6323-auxadc",
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.of_match_table = mt6323_auxadc_of_match,
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},
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.probe = mt6323_auxadc_probe,
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};
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module_platform_driver(mt6323_auxadc_driver);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("MediaTek MT6323 PMIC AUXADC Driver");
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