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spi: dt-bindings: qcom,spi-qup: convert to dtschema
Convert the Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) bindings to DT Schema. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Kuldeep Singh <singh.kuldeep87k@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220405063451.12011-7-krzysztof.kozlowski@linaro.org
This commit is contained in:
Krzysztof Kozlowski
Rob Herring
parent
92298ea34a
commit
d6a4371c3c
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Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
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The QUP core is an AHB slave that provides a common data path (an output FIFO
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and an input FIFO) for serial peripheral interface (SPI) mini-core.
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SPI in master mode supports up to 50MHz, up to four chip selects, programmable
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data path from 4 bits to 32 bits and numerous protocol variants.
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Required properties:
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- compatible: Should contain:
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"qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
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"qcom,spi-qup-v2.1.1" for 8974 and later
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"qcom,spi-qup-v2.2.1" for 8974 v2 and later.
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- reg: Should contain base register location and length
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- interrupts: Interrupt number used by this controller
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- clocks: Should contain the core clock and the AHB clock.
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- clock-names: Should be "core" for the core clock and "iface" for the
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AHB clock.
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- #address-cells: Number of cells required to define a chip select
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address on the SPI bus. Should be set to 1.
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- #size-cells: Should be zero.
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Optional properties:
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- spi-max-frequency: Specifies maximum SPI clock frequency,
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Units - Hz. Definition as per
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Documentation/devicetree/bindings/spi/spi-bus.txt
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- num-cs: total number of chipselects
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- cs-gpios: should specify GPIOs used for chipselects.
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The gpios will be referred to as reg = <index> in the SPI child
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nodes. If unspecified, a single SPI device without a chip
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select can be used.
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- dmas: Two DMA channel specifiers following the convention outlined
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in bindings/dma/dma.txt
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- dma-names: Names for the dma channels, if present. There must be at
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least one channel named "tx" for transmit and named "rx" for
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receive.
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SPI slave nodes must be children of the SPI master node and can contain
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properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
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Example:
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spi_8: spi@f9964000 { /* BLSP2 QUP2 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xf9964000 0x1000>;
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interrupts = <0 102 0>;
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spi-max-frequency = <19200000>;
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clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp1_bam 13>, <&blsp1_bam 12>;
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dma-names = "rx", "tx";
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pinctrl-names = "default";
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pinctrl-0 = <&spi8_default>;
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device@0 {
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compatible = "arm,pl022-dummy";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <19200000>;
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spi-cpol;
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};
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device@1 {
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compatible = "arm,pl022-dummy";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <1>; /* Chip select 1 */
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spi-max-frequency = <9600000>;
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spi-cpha;
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};
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device@2 {
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compatible = "arm,pl022-dummy";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <2>; /* Chip select 2 */
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spi-max-frequency = <19200000>;
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spi-cpol;
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spi-cpha;
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};
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device@3 {
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compatible = "arm,pl022-dummy";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <3>; /* Chip select 3 */
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spi-max-frequency = <19200000>;
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spi-cpol;
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spi-cpha;
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spi-cs-high;
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};
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};
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81
Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml
Normal file
81
Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml
Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/qcom,spi-qup.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
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maintainers:
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- Andy Gross <agross@kernel.org>
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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description:
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The QUP core is an AHB slave that provides a common data path (an output FIFO
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and an input FIFO) for serial peripheral interface (SPI) mini-core.
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SPI in master mode supports up to 50MHz, up to four chip selects,
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programmable data path from 4 bits to 32 bits and numerous protocol variants.
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allOf:
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- $ref: /schemas/spi/spi-controller.yaml#
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properties:
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compatible:
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enum:
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- qcom,spi-qup-v1.1.1 # for 8660, 8960 and 8064
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- qcom,spi-qup-v2.1.1 # for 8974 and later
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- qcom,spi-qup-v2.2.1 # for 8974 v2 and later
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: core
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- const: iface
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: tx
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- const: rx
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interrupts:
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maxItems: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- clocks
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- clock-names
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- interrupts
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-msm8996.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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spi@7575000 {
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x07575000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp1_spi1_default>;
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pinctrl-1 = <&blsp1_spi1_sleep>;
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dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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