From d691a96370b6cd7e684e4da1c473c09df963611b Mon Sep 17 00:00:00 2001 From: "Baek Kyu, Kim" Date: Tue, 20 Oct 2026 00:10:24 +0900 Subject: [PATCH] rtc: mpfs: Fix alarm register word order mpfs_rtc_readalarm() swaps the low and high words of the alarm time. The RTC core reads this value during device registration to initialize its alarm timer. This can populate the cached alarm and timer queue with an incorrect expiry time, or leave an enabled hardware alarm out of the timer queue if the decoded time appears to be in the past. Read the low 32 bits from ALARM_LOWER_REG and place the masked high 11 bits from ALARM_UPPER_REG in bits 42:32. This matches the layout used by mpfs_rtc_setalarm() and the low/high assembly in mpfs_rtc_readtime(), so the RTC core imports the programmed alarm time correctly during device registration. Fixes: 0b31d703598d ("rtc: Add driver for Microchip PolarFire SoC") Signed-off-by: Baek Kyu, Kim Reviewed-by: Conor Dooley Link: https://patch.msgid.link/20261019151024.2232338-1-pocj8ur4in@gmail.com Signed-off-by: Alexandre Belloni --- drivers/rtc/rtc-mpfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/rtc/rtc-mpfs.c b/drivers/rtc/rtc-mpfs.c index ece6de4a6adb..caabb50d3f9c 100644 --- a/drivers/rtc/rtc-mpfs.c +++ b/drivers/rtc/rtc-mpfs.c @@ -131,8 +131,8 @@ static int mpfs_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) alrm->enabled = mode & MODE_WAKE_EN; - time = (u64)readl(rtcdev->base + ALARM_LOWER_REG) << 32; - time |= (readl(rtcdev->base + ALARM_UPPER_REG) & ALARM_UPPER_MASK); + time = readl(rtcdev->base + ALARM_LOWER_REG); + time |= ((u64)readl(rtcdev->base + ALARM_UPPER_REG) & ALARM_UPPER_MASK) << 32; rtc_time64_to_tm(time, &alrm->time); return 0;