From f9c68b1c5be432e7e18039c3b23a1c107c9cb47f Mon Sep 17 00:00:00 2001 From: Chen Ni Date: Tue, 25 Nov 2025 09:47:40 +0800 Subject: [PATCH 1/7] drm/mediatek: mtk_hdmi_v2: Remove unneeded semicolon Remove unnecessary semicolons reported by Coccinelle/coccicheck and the semantic patch at scripts/coccinelle/misc/semicolon.cocci. Signed-off-by: Chen Ni Link: https://patchwork.kernel.org/project/dri-devel/patch/20251125014740.1059347-1-nichen@iscas.ac.cn/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi_v2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c index c272e1e74b7d..d510ca8cfc4a 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c @@ -746,7 +746,7 @@ static void mtk_hdmi_v2_change_video_resolution(struct mtk_hdmi *hdmi, case HDMI_COLORSPACE_YUV420: mtk_hdmi_yuv420_downsampling(hdmi, true); break; - }; + } } static void mtk_hdmi_v2_output_set_display_mode(struct mtk_hdmi *hdmi, @@ -1157,7 +1157,7 @@ static int mtk_hdmi_v2_hdmi_clear_infoframe(struct drm_bridge *bridge, case HDMI_INFOFRAME_TYPE_DRM: default: break; - }; + } return 0; } @@ -1185,7 +1185,7 @@ static int mtk_hdmi_v2_hdmi_write_infoframe(struct drm_bridge *bridge, default: dev_err(hdmi->dev, "Unsupported HDMI infoframe type %u\n", type); break; - }; + } return 0; } From 65155d1682db63ad3e1e54ccfc4b0d415616a38d Mon Sep 17 00:00:00 2001 From: Liankun Yang Date: Tue, 23 Dec 2025 14:16:52 +0800 Subject: [PATCH 2/7] drm/mediatek: Move DP training to hotplug thread By adjusting the order of link training and relocating it to HPD, link training can identify the usability of each lane in the current link. It also supports handling signal instability and weakness due to environmental issues, enabling the acquisition of a stable bandwidth for the current link. Subsequently, DP work can proceed based on the actual maximum bandwidth. It should training in the hpd event thread. Check the mode with lane count and link rate of training. If we're eDP and capabilities were already parsed we can skip reading again because eDP panels aren't hotpluggable hence the caps and training information won't ever change in a boot life Therefore, bridge typec judgment is required for edp training in atomic_enable function. `mtk_dp_parse_capabilities` is related to DP training, it is used in `mtk_dp_hpd_event_thread` before DP training, and then only used by eDP when read edid. -Modify part of in `mtk_dp_bridge_atomic_disable` if (mtk_dp->train_info.cable_plugged_in) { drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3); usleep_range(2000, 3000); } /* power off aux */ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, DP_PWR_STATE_BANDGAP_TPLL, DP_PWR_STATE_MASK); -Modify part of in `mtk_dp_aux_panel_poweron(mtk_dp, false);` if (pwron) { .... } else { /* power off panel */ drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3); usleep_range(2000, 3000); /* power off aux */ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, DP_PWR_STATE_BANDGAP_TPLL, DP_PWR_STATE_MASK); } The `mtk_dp_aux_panel_poweron` function fails to align. Within the `mtk_dp_hpd_event_thread`, if DP is disconnected, the `mtk_dp_aux_panel_poweron` function will write from `aux` to `DPRX`, causing a failure and thus preventing symmetry. This shows the current timings after the DP cable is plugged in, as well as the modified timings. current timings: Fix timings: mtk_dp_hpd_event_thread() mtk_dp_hpd_event_thread() (including DP link training) | | ... ... mtk_dp_bridge_mode_valid() mtk_dp_bridge_mode_valid() | ... ... mtk_dp_bridge_atomic_check() mtk_dp_bridge_atomic_check() | ... ... mtk_dp_bridge_atomic_enable() mtk_dp_bridge_atomic_enable() (including DP link training) PS: 1. "..." represents ommited steps; 2. `mtk_dp_bridge_mode_valid()` calculates the bandwidth using the current lane count and link rate, and then filters each mode to determine if it supports returning a status. 3. In the `drm_display_mode_to_videomode(&crtc_state->adjusted_mode, &mtk_dp->info.vm);` function, within the `mtk_dp_bridge_atomic_check()` function, `adjusted_mode` sets the currently selected display mode for the DRM. 4. DP link training tests the signal conditions of the link between DPTX and DPRX, and selects the lane count and link rate that meet the signal conditions. 5. For example, the platform support DP 4lane 5.4G, but panel A support DP 2lane 5.4G. This is a time sequence: a).Plug in panel A. According to the platform, it can output 4K60Hz. b).Timing mode set 4K 60Hz(Including in mtk_dp_bridge_atomic_check function). c).Atomic enable(Based on panel A ability, training pass 2lane 5.4G). d).Finally, due to 2lane 5.4G bandwidth limitation, the platform cannot output 4K 60Hz, resulting in a black sreen. If apply this patch. a).Plug in panel A. b).Training pass 2lane 5.4G c).Timing mode set 2K 60Hz(Based on the 2lane 5.4G bandwidth limit and including in mtk_dp_bridge_atomic_che Signed-off-by: Liankun Yang Link: https://patchwork.kernel.org/project/dri-devel/patch/20251223061755.7717-1-liankun.yang@mediatek.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dp.c | 57 ++++++++++++++++++++----------- 1 file changed, 38 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c index b0b1e158600f..5e67dab6e2e9 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -1976,6 +1976,7 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev) struct mtk_dp *mtk_dp = dev; unsigned long flags; u32 status; + int ret; if (mtk_dp->need_debounce && mtk_dp->train_info.cable_plugged_in) msleep(100); @@ -1994,9 +1995,28 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev) memset(&mtk_dp->info.audio_cur_cfg, 0, sizeof(mtk_dp->info.audio_cur_cfg)); + mtk_dp->enabled = false; + /* power off aux */ + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, + DP_PWR_STATE_BANDGAP_TPLL, + DP_PWR_STATE_MASK); + mtk_dp->need_debounce = false; mod_timer(&mtk_dp->debounce_timer, jiffies + msecs_to_jiffies(100) - 1); + } else { + mtk_dp_aux_panel_poweron(mtk_dp, true); + + ret = mtk_dp_parse_capabilities(mtk_dp); + if (ret) + drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n"); + + /* Training */ + ret = mtk_dp_training(mtk_dp); + if (ret) + drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret); + + mtk_dp->enabled = true; } } @@ -2168,7 +2188,8 @@ static const struct drm_edid *mtk_dp_edid_read(struct drm_bridge *bridge, * Parse capability here to let atomic_get_input_bus_fmts and * mode_valid use the capability to calculate sink bitrates. */ - if (mtk_dp_parse_capabilities(mtk_dp)) { + if (mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP && + mtk_dp_parse_capabilities(mtk_dp)) { drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n"); drm_edid_free(drm_edid); drm_edid = NULL; @@ -2366,13 +2387,15 @@ static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge, return; } - mtk_dp_aux_panel_poweron(mtk_dp, true); + if (mtk_dp->data->bridge_type == DRM_MODE_CONNECTOR_eDP) { + mtk_dp_aux_panel_poweron(mtk_dp, true); - /* Training */ - ret = mtk_dp_training(mtk_dp); - if (ret) { - drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret); - goto power_off_aux; + /* Training */ + ret = mtk_dp_training(mtk_dp); + if (ret) { + drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret); + goto power_off_aux; + } } ret = mtk_dp_video_config(mtk_dp); @@ -2392,7 +2415,9 @@ static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge, sizeof(mtk_dp->info.audio_cur_cfg)); } - mtk_dp->enabled = true; + if (mtk_dp->data->bridge_type == DRM_MODE_CONNECTOR_eDP) + mtk_dp->enabled = true; + mtk_dp_update_plugged_status(mtk_dp); return; @@ -2407,21 +2432,15 @@ static void mtk_dp_bridge_atomic_disable(struct drm_bridge *bridge, { struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge); - mtk_dp->enabled = false; + if (mtk_dp->data->bridge_type == DRM_MODE_CONNECTOR_eDP) { + mtk_dp->enabled = false; + mtk_dp_aux_panel_poweron(mtk_dp, false); + } + mtk_dp_update_plugged_status(mtk_dp); mtk_dp_video_enable(mtk_dp, false); mtk_dp_audio_mute(mtk_dp, true); - if (mtk_dp->train_info.cable_plugged_in) { - drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3); - usleep_range(2000, 3000); - } - - /* power off aux */ - mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, - DP_PWR_STATE_BANDGAP_TPLL, - DP_PWR_STATE_MASK); - /* SDP path reset sw*/ mtk_dp_sdp_path_reset(mtk_dp); From 24abe1f238e7d7ac56be6374c52a3c13dab84f69 Mon Sep 17 00:00:00 2001 From: Abhishek Rajput Date: Tue, 23 Dec 2025 15:24:34 +0530 Subject: [PATCH 3/7] drm/mediatek: Convert legacy DRM logging to drm_* helpers in mtk_crtc.c Replace DRM_ERROR() and DRM_DEBUG_DRIVER() calls in drivers/gpu/drm/mediatek/mtk_crtc.c with the corresponding drm_err() and drm_dbg_driver() helpers. The drm_*() logging helpers take a struct drm_device * argument, allowing the DRM core to prefix log messages with the correct device name and instance. This is required to correctly distinguish log messages on systems with multiple GPUs. This change aligns the Mediatek DRM driver with the DRM TODO item: "Convert logging to drm_* functions with drm_device parameter". Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202512220515.z3QybJ8I-lkp@intel.com/ Signed-off-by: Abhishek Rajput Reviewed-by: CK Hu Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20251223095434.492041-1-abhiraj21put@gmail.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_crtc.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c index 991cdb3d7d5f..6ad712c0339a 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -225,13 +225,14 @@ static void mtk_crtc_mode_set_nofb(struct drm_crtc *crtc) static int mtk_crtc_ddp_clk_enable(struct mtk_crtc *mtk_crtc) { + struct drm_device *dev = mtk_crtc->base.dev; int ret; int i; for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]); if (ret) { - DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); + drm_err(dev, "Failed to enable clock %d: %d\n", i, ret); goto err; } } @@ -343,6 +344,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_crtc) struct drm_connector *connector; struct drm_encoder *encoder; struct drm_connector_list_iter conn_iter; + struct drm_device *dev = mtk_crtc->base.dev; unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; int ret; int i; @@ -371,19 +373,19 @@ static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_crtc) ret = pm_runtime_resume_and_get(crtc->dev->dev); if (ret < 0) { - DRM_ERROR("Failed to enable power domain: %d\n", ret); + drm_err(dev, "Failed to enable power domain: %d\n", ret); return ret; } ret = mtk_mutex_prepare(mtk_crtc->mutex); if (ret < 0) { - DRM_ERROR("Failed to enable mutex clock: %d\n", ret); + drm_err(dev, "Failed to enable mutex clock: %d\n", ret); goto err_pm_runtime_put; } ret = mtk_crtc_ddp_clk_enable(mtk_crtc); if (ret < 0) { - DRM_ERROR("Failed to enable component clocks: %d\n", ret); + drm_err(dev, "Failed to enable component clocks: %d\n", ret); goto err_mutex_unprepare; } @@ -648,11 +650,12 @@ static void mtk_crtc_ddp_irq(void *data) struct mtk_drm_private *priv = crtc->dev->dev_private; #if IS_REACHABLE(CONFIG_MTK_CMDQ) + struct drm_device *dev = mtk_crtc->base.dev; if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan) mtk_crtc_ddp_config(crtc, NULL); else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0) - DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n", - drm_crtc_index(&mtk_crtc->base)); + drm_err(dev, "mtk_crtc %d CMDQ execute command timeout!\n", + drm_crtc_index(&mtk_crtc->base)); #else if (!priv->data->shadow_register) mtk_crtc_ddp_config(crtc, NULL); @@ -776,9 +779,10 @@ static void mtk_crtc_atomic_enable(struct drm_crtc *crtc, { struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc); struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; + struct drm_device *dev = mtk_crtc->base.dev; int ret; - DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); + drm_dbg_driver(dev, "%s %d\n", __func__, crtc->base.id); ret = mtk_ddp_comp_power_on(comp); if (ret < 0) { @@ -803,9 +807,10 @@ static void mtk_crtc_atomic_disable(struct drm_crtc *crtc, { struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc); struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; + struct drm_device *dev = mtk_crtc->base.dev; int i; - DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); + drm_dbg_driver(dev, "%s %d\n", __func__, crtc->base.id); if (!mtk_crtc->enabled) return; @@ -845,10 +850,11 @@ static void mtk_crtc_atomic_begin(struct drm_crtc *crtc, crtc); struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state); struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc); + struct drm_device *dev = mtk_crtc->base.dev; unsigned long flags; if (mtk_crtc->event && mtk_crtc_state->base.event) - DRM_ERROR("new event while there is still a pending event\n"); + drm_err(dev, "new event while there is still a pending event\n"); if (mtk_crtc_state->base.event) { mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc); From 8b00951402f7420365b5697269b190f616bd116a Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 8 Jan 2026 11:19:59 +0100 Subject: [PATCH 4/7] drm/mediatek: mtk_dsi: Add support for High Speed (HS) mode Up until now, the MediaTek DSI Controller has always been working in Low Power Mode (LPM), as this driver has always ignored the MIPI_DSI_MSG_USE_LPM flag hence never setting HS mode. In the current state of the driver the only thing that is needed to add support for DSI High Speed (HS) transmit is to simply set the "HSTX" config bit in the configuration register. Check if flag MIPI_DSI_MSG_USE_LPM is set and, if not, set HSTX. Signed-off-by: AngeloGioacchino Del Regno Tested-by: Gary Bisson Reviewed-by: CK Hu Link: https://patchwork.kernel.org/project/dri-devel/patch/20260108101959.14872-1-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dsi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 0e2bcd5f67b7..cad7d1e26418 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -152,6 +152,7 @@ #define SHORT_PACKET 0 #define LONG_PACKET 2 #define BTA BIT(2) +#define HSTX BIT(3) #define DATA_ID GENMASK(15, 8) #define DATA_0 GENMASK(23, 16) #define DATA_1 GENMASK(31, 24) @@ -1080,6 +1081,9 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg) else config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET; + if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) + config |= HSTX; + if (msg->tx_len > 2) { cmdq_size = 1 + (msg->tx_len + 3) / 4; cmdq_off = 4; From 01c430b1cfa8a6ce0cbf99edc38dac3bfc51e464 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 17 Dec 2025 11:19:00 +0100 Subject: [PATCH 5/7] dt-bindings: phy: mediatek,hdmi-phy: Fix clock output names for MT8195 For all of the HDMI PHYs compatible with the one found on MT8195 the output clock has a different datasheet name and specifically it is called "hdmi_txpll", differently from the older HDMI PHYs which output block is called "hdmitx_dig_cts". Replace clock output name string check by max item number one to allow the new name on all of the HDMI PHY IPs that are perfectly compatible with MT8195. [Louis-Alexis Eyraud: split patch, addressed previous feedback from mailing list, and reworded description] Fixes: c78fe548b062 ("dt-bindings: phy: mediatek: hdmi-phy: Add mt8195 compatible") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) Signed-off-by: Louis-Alexis Eyraud Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20251217-mtk-genio-evk-hdmi-support-v2-1-a994976bb39a@collabora.com/ Signed-off-by: Chun-Kuang Hu --- Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml index f3a8b0b745d1..10f1d9326f18 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml @@ -42,8 +42,7 @@ properties: - const: pll_ref clock-output-names: - items: - - const: hdmitx_dig_cts + maxItems: 1 "#phy-cells": const: 0 From 8a25ab7a57e67baddee185c3fd565df1062e4807 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 17 Dec 2025 11:19:01 +0100 Subject: [PATCH 6/7] dt-bindings: phy: mediatek,hdmi-phy: Add support for MT8188 SoC Add compatible string for the HDMI PHY IP on MT8188 SoC, that is compatible with the one found on MT8195 SoC. Signed-off-by: Louis-Alexis Eyraud Reviewed-by: Rob Herring (Arm) Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20251217-mtk-genio-evk-hdmi-support-v2-2-a994976bb39a@collabora.com/ Signed-off-by: Chun-Kuang Hu --- Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml index 10f1d9326f18..cd4ac42ee45e 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml @@ -26,6 +26,10 @@ properties: - enum: - mediatek,mt7623-hdmi-phy - const: mediatek,mt2701-hdmi-phy + - items: + - enum: + - mediatek,mt8188-hdmi-phy + - const: mediatek,mt8195-hdmi-phy - const: mediatek,mt2701-hdmi-phy - const: mediatek,mt8173-hdmi-phy - const: mediatek,mt8195-hdmi-phy From 79643afdd985ee14f9dddd66da262314f04d1640 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Wed, 17 Dec 2025 11:19:02 +0100 Subject: [PATCH 7/7] dt-bindings: phy: mediatek,hdmi-phy: Document extra clocks for MT8195 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT8195's HDMI PHY block has 4 clocks instead of just a single one. Describe the extra clocks for it. Signed-off-by: Nícolas F. R. A. Prado Signed-off-by: Louis-Alexis Eyraud Reviewed-by: Rob Herring (Arm) Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20251217-mtk-genio-evk-hdmi-support-v2-3-a994976bb39a@collabora.com/ Signed-off-by: Chun-Kuang Hu --- .../bindings/phy/mediatek,hdmi-phy.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml index cd4ac42ee45e..ac93069f4801 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml @@ -38,12 +38,20 @@ properties: maxItems: 1 clocks: + minItems: 1 items: - description: PLL reference clock + - description: HDMI 26MHz clock + - description: HDMI PLL1 clock + - description: HDMI PLL2 clock clock-names: + minItems: 1 items: - const: pll_ref + - const: 26m + - const: pll1 + - const: pll2 clock-output-names: maxItems: 1 @@ -79,6 +87,20 @@ required: - "#phy-cells" - "#clock-cells" +allOf: + - if: + not: + properties: + compatible: + contains: + const: mediatek,mt8195-hdmi-phy + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + additionalProperties: false examples: