github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-06-04 04:23:35 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/amd/display: Revert "Improve x86 and dmub ips handshake"

Browse Source 
This reverts commit 1288d70208.

Causes intermittent hangs during reboot stress testing.

Reviewed-by: Duncan Ma <duncan.ma@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas 2023-10-03 12:18:44 -04:00 committed by Alex Deucher
parent 543068f0e3
commit d5f9a92bd1
11 changed files with 27 additions and 129 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
View File

@ -808,34 +808,6 @@ static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)
}
}
static void dcn35_set_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
struct dc *dc = clk_mgr_base->ctx->dc;
uint32_t val = dcn35_smu_read_ips_scratch(clk_mgr);
if (dc->config.disable_ips == 0) {
val |= DMUB_IPS1_ALLOW_MASK;
val |= DMUB_IPS2_ALLOW_MASK;
} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {
val = val & ~DMUB_IPS1_ALLOW_MASK;
val = val & ~DMUB_IPS2_ALLOW_MASK;
} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {
val |= DMUB_IPS1_ALLOW_MASK;
val = val & ~DMUB_IPS2_ALLOW_MASK;
} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {
val |= DMUB_IPS1_ALLOW_MASK;
val |= DMUB_IPS2_ALLOW_MASK;
}
if (!allow_idle) {
val = val & ~DMUB_IPS1_ALLOW_MASK;
val = val & ~DMUB_IPS2_ALLOW_MASK;
}
dcn35_smu_write_ips_scratch(clk_mgr, val);
}
static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
@ -855,13 +827,6 @@ static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)
return ips_supported;
}
static uint32_t dcn35_get_idle_state(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
return dcn35_smu_read_ips_scratch(clk_mgr);
}
static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)
{
dcn35_init_clocks(clk_mgr);
@ -949,8 +914,6 @@ static struct clk_mgr_funcs dcn35_funcs = {
.set_low_power_state = dcn35_set_low_power_state,
.exit_low_power_state = dcn35_exit_low_power_state,
.is_ips_supported = dcn35_is_ips_supported,
.set_idle_state = dcn35_set_idle_state,
.get_idle_state = dcn35_get_idle_state
};
struct clk_mgr_funcs dcn35_fpga_funcs = {

14
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
View File

@ -444,9 +444,9 @@ void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *cl
enable);
}
int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)
void dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)
{
return dcn35_smu_send_msg_with_param(
dcn35_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_DispPsrExit,
0);
@ -459,13 +459,3 @@ int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr)
VBIOSSMC_MSG_QueryIPS2Support,
0);
}
void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param)
{
REG_WRITE(MP1_SMN_C2PMSG_71, param);
}
uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr)
{
return REG_READ(MP1_SMN_C2PMSG_71);
}

4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
View File

@ -194,10 +194,8 @@ void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zst
void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);
void dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);
int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr);
int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);
int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr);
void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param);
uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr);
#endif /* DAL_DC_35_SMU_H_ */

2
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -975,8 +975,6 @@ struct dc_debug_options {
bool replay_skip_crtc_disabled;
bool ignore_pg;/*do nothing, let pmfw control it*/
bool psp_disabled_wa;
unsigned int ips2_eval_delay_us;
unsigned int ips2_entry_delay_us;
};
struct gpu_info_soc_bounding_box_v1_0;

57
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
View File

@ -1100,64 +1100,31 @@ void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)
cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle;
if (allow_idle) {
if (dc->hwss.set_idle_state)
dc->hwss.set_idle_state(dc, true);
}
dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
if (allow_idle)
udelay(500);
}
void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
{
uint32_t allow_state = 0;
uint32_t commit_state = 0;
if (dc->debug.dmcub_emulation)
return;
if (!dc->idle_optimizations_allowed)
return;
if (dc->hwss.get_idle_state &&
dc->hwss.set_idle_state &&
dc->clk_mgr->funcs->exit_low_power_state) {
// Tell PMFW to exit low power state
if (dc->clk_mgr->funcs->exit_low_power_state)
dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
allow_state = dc->hwss.get_idle_state(dc);
dc->hwss.set_idle_state(dc, false);
// Wait for dmcub to load up
dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);
if (allow_state & DMUB_IPS2_ALLOW_MASK) {
// Wait for evaluation time
udelay(dc->debug.ips2_eval_delay_us);
commit_state = dc->hwss.get_idle_state(dc);
if (commit_state & DMUB_IPS2_COMMIT_MASK) {
// Tell PMFW to exit low power state
dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
// Notify dmcub disallow idle
dc_dmub_srv_notify_idle(dc, false);
// Wait for IPS2 entry upper bound
udelay(dc->debug.ips2_entry_delay_us);
dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
do {
commit_state = dc->hwss.get_idle_state(dc);
} while (commit_state & DMUB_IPS2_COMMIT_MASK);
if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))
ASSERT(0);
return;
}
}
dc_dmub_srv_notify_idle(dc, false);
if (allow_state & DMUB_IPS1_ALLOW_MASK) {
do {
commit_state = dc->hwss.get_idle_state(dc);
} while (commit_state & DMUB_IPS1_COMMIT_MASK);
}
}
if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))
ASSERT(0);
// Confirm dmu is powered up
dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);
}

2
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_init.c
View File

@ -120,8 +120,6 @@ static const struct hw_sequencer_funcs dcn35_funcs = {
.calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate,
.block_power_control = dcn35_block_power_control,
.root_clock_control = dcn35_root_clock_control,
.set_idle_state = dcn35_set_idle_state,
.get_idle_state = dcn35_get_idle_state
};
static const struct hwseq_private_funcs dcn35_private_funcs = {

2
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
View File

@ -748,8 +748,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_z10 = false,
.ignore_pg = true,
.psp_disabled_wa = true,
.ips2_eval_delay_us = 200,
.ips2_entry_delay_us = 400
};
static const struct dc_panel_config panel_config_defaults = {

30
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
View File

@ -652,10 +652,18 @@ bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable)
// TODO: review other cases when idle optimization is allowed
if (!enable) {
// Tell PMFW to exit low power state
if (dc->clk_mgr->funcs->exit_low_power_state)
dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);
}
dc_dmub_srv_notify_idle(dc, enable);
if (!enable)
dc_dmub_srv_exit_low_power_state(dc);
else
dc_dmub_srv_notify_idle(dc, enable);
dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);
return true;
}
@ -1189,19 +1197,3 @@ void dcn35_optimize_bandwidth(
dc->hwss.root_clock_control(dc, &pg_update_state, false);
}
}
void dcn35_set_idle_state(const struct dc *dc, bool allow_idle)
{
// TODO: Find a more suitable communcation
if (dc->clk_mgr->funcs->set_idle_state)
dc->clk_mgr->funcs->set_idle_state(dc->clk_mgr, allow_idle);
}
uint32_t dcn35_get_idle_state(const struct dc *dc)
{
// TODO: Find a more suitable communcation
if (dc->clk_mgr->funcs->get_idle_state)
return dc->clk_mgr->funcs->get_idle_state(dc->clk_mgr);
return 0;
}

3
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
View File

@ -81,7 +81,4 @@ void dcn35_dsc_pg_control(
struct dce_hwseq *hws,
unsigned int dsc_inst,
bool power_on);
void dcn35_set_idle_state(const struct dc *dc, bool allow_idle);
uint32_t dcn35_get_idle_state(const struct dc *dc);
#endif /* __DC_HWSS_DCN35_H__ */

3
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
View File

@ -418,8 +418,7 @@ struct hw_sequencer_funcs {
struct pg_block_update *update_state, bool power_on);
void (*root_clock_control)(struct dc *dc,
struct pg_block_update *update_state, bool power_on);
void (*set_idle_state)(const struct dc *dc, bool allow_idle);
uint32_t (*get_idle_state)(const struct dc *dc);
bool (*is_pipe_topology_transition_seamless)(struct dc *dc,
const struct dc_state *cur_ctx,
const struct dc_state *new_ctx);

2
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
View File

@ -262,8 +262,6 @@ struct clk_mgr_funcs {
void (*set_low_power_state)(struct clk_mgr *clk_mgr);
void (*exit_low_power_state)(struct clk_mgr *clk_mgr);
bool (*is_ips_supported)(struct clk_mgr *clk_mgr);
void (*set_idle_state)(struct clk_mgr *clk_mgr, bool allow_idle);
uint32_t (*get_idle_state)(struct clk_mgr *clk_mgr);
void (*init_clocks)(struct clk_mgr *clk_mgr);