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media: i2c: st-mipid02: fix mipid02_stream_enable error handling
Following addition of cascaded s_stream call within mipid02_stream_enable and mipid02_stream_disable, the mipid02_stream_enable error handling must be fixed to simply disable the clocks & data lanes without also calling again the s_stream of the source subdev. Moreover, main control registers are reset to 0 for all cases of error within the mipid02_stream_enable even if they haven't yet been written. Correct this behavior by simply returning an error when register clear are not necessary. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
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commit
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@ -480,7 +480,7 @@ static int mipid02_stream_enable(struct mipid02_dev *bridge)
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int ret = -EINVAL;
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if (!bridge->s_subdev)
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goto error;
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return ret;
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memset(&bridge->r, 0, sizeof(bridge->r));
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@ -490,13 +490,13 @@ static int mipid02_stream_enable(struct mipid02_dev *bridge)
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/* build registers content */
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ret = mipid02_configure_from_rx(bridge, fmt);
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if (ret)
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goto error;
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return ret;
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ret = mipid02_configure_from_tx(bridge);
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if (ret)
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goto error;
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return ret;
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ret = mipid02_configure_from_code(bridge, fmt);
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if (ret)
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goto error;
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return ret;
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v4l2_subdev_unlock_state(state);
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@ -531,8 +531,10 @@ static int mipid02_stream_enable(struct mipid02_dev *bridge)
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return 0;
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error:
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cci_write(bridge->regmap, MIPID02_CLK_LANE_REG1, 0, &ret);
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cci_write(bridge->regmap, MIPID02_DATA_LANE0_REG1, 0, &ret);
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cci_write(bridge->regmap, MIPID02_DATA_LANE1_REG1, 0, &ret);
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dev_err(&client->dev, "failed to stream on %d", ret);
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mipid02_stream_disable(bridge);
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return ret;
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}
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