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arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE
QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the first SE, which supports a 4-wire UART configuration suitable for applications such as HS-UART. Note that the required initialization for this SE is not handled by the bootloader. Therefore, add the SE node in the device tree but keep it reserved. Enable it once Linux gains support for configuring the SE, allowing to use in relevant RDPs. Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250812-ipq5424_hsuart-v4-1-f1faa7704ea9@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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@ -224,6 +224,13 @@ data-pins {
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};
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};
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uart0_pins: uart0-default-state {
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pins = "gpio10", "gpio11", "gpio12", "gpio13";
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function = "uart0";
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drive-strength = <8>;
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bias-pull-down;
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};
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pcie2_default_state: pcie2-default-state {
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pins = "gpio31";
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function = "gpio";
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@ -239,6 +246,17 @@ pcie3_default_state: pcie3-default-state {
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};
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};
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&uart0 {
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pinctrl-0 = <&uart0_pins>;
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pinctrl-names = "default";
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/*
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* The required initialization for this SE is not handled by the
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* bootloader. Therefore, keep the device in "reserved" state until
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* linux gains support for configuring the SE.
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*/
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status = "reserved";
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};
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&uart1 {
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pinctrl-0 = <&uart1_pins>;
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pinctrl-names = "default";
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@ -442,6 +442,15 @@ qupv3: geniqup@1ac0000 {
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#address-cells = <2>;
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#size-cells = <2>;
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uart0: serial@1a80000 {
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compatible = "qcom,geni-uart";
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reg = <0 0x01a80000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_UART0_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart1: serial@1a84000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0 0x01a84000 0 0x4000>;
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