arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE

QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the
first SE, which supports a 4-wire UART configuration suitable for
applications such as HS-UART.

Note that the required initialization for this SE is not handled by the
bootloader. Therefore, add the SE node in the device tree but keep it
reserved. Enable it once Linux gains support for configuring the SE,
allowing to use in relevant RDPs.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250812-ipq5424_hsuart-v4-1-f1faa7704ea9@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Kathiravan Thirumoorthy 2025-08-12 16:02:41 +05:30 committed by Bjorn Andersson
parent 393d69df0f
commit d56ddcee01
2 changed files with 27 additions and 0 deletions

View File

@ -224,6 +224,13 @@ data-pins {
};
};
uart0_pins: uart0-default-state {
pins = "gpio10", "gpio11", "gpio12", "gpio13";
function = "uart0";
drive-strength = <8>;
bias-pull-down;
};
pcie2_default_state: pcie2-default-state {
pins = "gpio31";
function = "gpio";
@ -239,6 +246,17 @@ pcie3_default_state: pcie3-default-state {
};
};
&uart0 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
/*
* The required initialization for this SE is not handled by the
* bootloader. Therefore, keep the device in "reserved" state until
* linux gains support for configuring the SE.
*/
status = "reserved";
};
&uart1 {
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";

View File

@ -442,6 +442,15 @@ qupv3: geniqup@1ac0000 {
#address-cells = <2>;
#size-cells = <2>;
uart0: serial@1a80000 {
compatible = "qcom,geni-uart";
reg = <0 0x01a80000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_UART0_CLK>;
clock-names = "se";
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart1: serial@1a84000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x01a84000 0 0x4000>;