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ASoC: dt-bindings: fsl,sai: Convert format to json-schema
Convert the NXP SAI binding to DT schema format using json-schema. The Synchronous Audio Interface (SAI) provides an interface that supports full-duplex serial interfaces with frame synchronization formats such as I2S, AC97, TDM, and codec/DSP interfaces. Beside conversion, 'fsl,shared-interrupt' and '#sound-dai-cells' are added for they are already used by some dts. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/1659443394-9838-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
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Shengjiu Wang
Mark Brown
parent
4e6bedd3c3
commit
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216
Documentation/devicetree/bindings/sound/fsl,sai.yaml
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216
Documentation/devicetree/bindings/sound/fsl,sai.yaml
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@ -0,0 +1,216 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/fsl,sai.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Synchronous Audio Interface (SAI).
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maintainers:
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- Shengjiu Wang <shengjiu.wang@nxp.com>
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description: |
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The SAI is based on I2S module that used communicating with audio codecs,
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which provides a synchronous audio interface that supports fullduplex
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serial interfaces with frame synchronization such as I2S, AC97, TDM, and
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codec/DSP interfaces.
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,vf610-sai
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- fsl,imx6sx-sai
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- fsl,imx6ul-sai
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- fsl,imx7ulp-sai
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- fsl,imx8mq-sai
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- fsl,imx8qm-sai
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- fsl,imx8ulp-sai
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- items:
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- enum:
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- fsl,imx8mm-sai
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- fsl,imx8mn-sai
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- fsl,imx8mp-sai
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- const: fsl,imx8mq-sai
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: receive and transmit interrupt
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dmas:
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maxItems: 2
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dma-names:
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maxItems: 2
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clocks:
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items:
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- description: The ipg clock for register access
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- description: master clock source 0 (obsoleted)
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- description: master clock source 1
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- description: master clock source 2
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- description: master clock source 3
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- description: PLL clock source for 8kHz series
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- description: PLL clock source for 11kHz series
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minItems: 4
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clock-names:
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oneOf:
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- items:
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- const: bus
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- const: mclk0
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- const: mclk1
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- const: mclk2
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- const: mclk3
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- const: pll8k
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- const: pll11k
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minItems: 4
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- items:
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- const: bus
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- const: mclk1
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- const: mclk2
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- const: mclk3
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- const: pll8k
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- const: pll11k
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minItems: 4
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lsb-first:
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description: |
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Configures whether the LSB or the MSB is transmitted
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first for the fifo data. If this property is absent,
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the MSB is transmitted first as default, or the LSB
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is transmitted first.
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type: boolean
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big-endian:
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description: |
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required if all the SAI registers are big-endian rather than little-endian.
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type: boolean
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fsl,sai-synchronous-rx:
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description: |
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SAI will work in the synchronous mode (sync Tx with Rx) which means
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both the transmitter and the receiver will send and receive data by
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following receiver's bit clocks and frame sync clocks.
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type: boolean
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fsl,sai-asynchronous:
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description: |
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SAI will work in the asynchronous mode, which means both transmitter
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and receiver will send and receive data by following their own bit clocks
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and frame sync clocks separately.
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If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
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default synchronous mode (sync Rx with Tx) will be used, which means both
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transmitter and receiver will send and receive data by following clocks
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of transmitter.
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type: boolean
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fsl,dataline:
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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description: |
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Configure the dataline. It has 3 value for each configuration
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maxItems: 16
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items:
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items:
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- description: format Default(0), I2S(1) or PDM(2)
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enum: [0, 1, 2]
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- description: dataline mask for 'rx'
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- description: dataline mask for 'tx'
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fsl,sai-mclk-direction-output:
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description: SAI will output the SAI MCLK clock.
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type: boolean
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fsl,shared-interrupt:
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description: Interrupt is shared with other modules.
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type: boolean
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"#sound-dai-cells":
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const: 0
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description: optional, some dts node didn't add it.
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: fsl,vf610-sai
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then:
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properties:
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dmas:
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items:
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- description: DMA controller phandle and request line for TX
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- description: DMA controller phandle and request line for RX
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dma-names:
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items:
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- const: tx
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- const: rx
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else:
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properties:
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dmas:
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items:
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- description: DMA controller phandle and request line for RX
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- description: DMA controller phandle and request line for TX
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dma-names:
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items:
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- const: rx
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- const: tx
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- if:
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required:
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- fsl,sai-asynchronous
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then:
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properties:
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fsl,sai-synchronous-rx: false
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required:
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- compatible
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- reg
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- interrupts
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- dmas
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- dma-names
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/vf610-clock.h>
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sai2: sai@40031000 {
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compatible = "fsl,vf610-sai";
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reg = <0x40031000 0x1000>;
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interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2_1>;
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clocks = <&clks VF610_CLK_PLATFORM_BUS>,
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<&clks VF610_CLK_SAI2>,
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<&clks 0>, <&clks 0>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dma-names = "tx", "rx";
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dmas = <&edma0 0 21>,
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<&edma0 0 20>;
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big-endian;
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lsb-first;
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/imx8mm-clock.h>
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sai1: sai@30010000 {
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compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
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reg = <0x30010000 0x10000>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
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<&clk IMX8MM_CLK_DUMMY>,
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<&clk IMX8MM_CLK_SAI1_ROOT>,
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<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
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clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
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dma-names = "rx", "tx";
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fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
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#sound-dai-cells = <0>;
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};
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@ -1,95 +0,0 @@
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Freescale Synchronous Audio Interface (SAI).
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The SAI is based on I2S module that used communicating with audio codecs,
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which provides a synchronous audio interface that supports fullduplex
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serial interfaces with frame synchronization such as I2S, AC97, TDM, and
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codec/DSP interfaces.
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Required properties:
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- compatible : Compatible list, contains "fsl,vf610-sai",
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"fsl,imx6sx-sai", "fsl,imx6ul-sai",
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"fsl,imx7ulp-sai", "fsl,imx8mq-sai",
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"fsl,imx8qm-sai", "fsl,imx8mm-sai",
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"fsl,imx8mn-sai", "fsl,imx8mp-sai", or
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"fsl,imx8ulp-sai".
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- reg : Offset and length of the register set for the device.
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- clocks : Must contain an entry for each entry in clock-names.
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- clock-names : Must include the "bus" for register access and
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"mclk1", "mclk2", "mclk3" for bit clock and frame
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clock providing.
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"pll8k", "pll11k" are optional, they are the clock
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source for root clock, one is for 8kHz series rates
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another one is for 11kHz series rates.
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- dmas : Generic dma devicetree binding as described in
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Documentation/devicetree/bindings/dma/dma.txt.
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- dma-names : Two dmas have to be defined, "tx" and "rx".
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- pinctrl-names : Must contain a "default" entry.
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- pinctrl-NNN : One property must exist for each entry in
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pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
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for details of the property values.
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- lsb-first : Configures whether the LSB or the MSB is transmitted
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first for the fifo data. If this property is absent,
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the MSB is transmitted first as default, or the LSB
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is transmitted first.
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- fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
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that SAI will work in the synchronous mode (sync Tx
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with Rx) which means both the transmitter and the
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receiver will send and receive data by following
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receiver's bit clocks and frame sync clocks.
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- fsl,sai-asynchronous: This is a boolean property. If present, indicating
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that SAI will work in the asynchronous mode, which
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means both transmitter and receiver will send and
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receive data by following their own bit clocks and
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frame sync clocks separately.
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- fsl,dataline : configure the dataline. it has 3 value for each configuration
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first one means the type: I2S(1) or PDM(2)
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second one is dataline mask for 'rx'
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third one is dataline mask for 'tx'.
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for example: fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
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it means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
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rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
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Optional properties:
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- big-endian : Boolean property, required if all the SAI
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registers are big-endian rather than little-endian.
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Optional properties (for mx6ul):
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- fsl,sai-mclk-direction-output: This is a boolean property. If present,
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indicates that SAI will output the SAI MCLK clock.
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Note:
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- If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
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default synchronous mode (sync Rx with Tx) will be used, which means both
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transmitter and receiver will send and receive data by following clocks
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of transmitter.
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- fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.
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Example:
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sai2: sai@40031000 {
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compatible = "fsl,vf610-sai";
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reg = <0x40031000 0x1000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2_1>;
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clocks = <&clks VF610_CLK_PLATFORM_BUS>,
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<&clks VF610_CLK_SAI2>,
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<&clks 0>, <&clks 0>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dma-names = "tx", "rx";
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dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
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<&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
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big-endian;
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lsb-first;
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};
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