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drm/amd/display: Revert wait vblank on update dpp clock

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[Why]
This change only fix dpp clock switch to lower case.
New solution later can fix both case, which is "dc: skip
program clock when allow seamless boot"

[How]
This reverts commit "dc: wait vblank when stream enabled
and update dpp clock"

Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lewis Huang 2021-04-13 07:02:28 +08:00 committed by Alex Deucher
parent 99c248c41c
commit d5433a9f69
3 changed files with 1 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
View File

@ -128,7 +128,7 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
struct dc *dc = clk_mgr_base->ctx->dc;
int display_count, i;
int display_count;
bool update_dppclk = false;
bool update_dispclk = false;
bool dpp_clock_lowered = false;
@ -210,14 +210,6 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
clk_mgr_base->clks.dppclk_khz,
safe_to_lower);
for (i = 0; i < context->stream_count; i++) {
if (context->streams[i]->signal == SIGNAL_TYPE_EDP &&
context->streams[i]->apply_seamless_boot_optimization) {
dc_wait_for_vblank(dc, context->streams[i]);
break;
}
}
clk_mgr_base->clks.actual_dppclk_khz =
rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

13
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -3219,19 +3219,6 @@ void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
}
}
void dc_wait_for_vblank(struct dc *dc, struct dc_stream_state *stream)
{
int i;
for (i = 0; i < dc->res_pool->pipe_count; i++)
if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
struct timing_generator *tg =
dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;
tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
break;
}
}
void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
{
info->displayClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;

1
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -719,7 +719,6 @@ void dc_init_callbacks(struct dc *dc,
void dc_deinit_callbacks(struct dc *dc);
void dc_destroy(struct dc **dc);
void dc_wait_for_vblank(struct dc *dc, struct dc_stream_state *stream);
/*******************************************************************************
* Surface Interfaces
******************************************************************************/