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drm/i915/fbc: Apply Wa_14025769978

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Disable cache read setting in the cacheability configuration
register as per the wa recommendation

Bspec: 79482, 74722, 68881
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patch.msgid.link/20251127115349.249120-4-vinod.govindapillai@intel.com
This commit is contained in:
Vinod Govindapillai 2025-11-27 13:53:49 +02:00
parent 0b806d62fd
commit d4ee41f9e1
3 changed files with 11 additions and 2 deletions
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2
drivers/gpu/drm/i915/display/intel_display_wa.c
View File

@ -72,6 +72,8 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
return IS_DISPLAY_VERx100(display, 1100, 1400);
case INTEL_DISPLAY_WA_15018326506:
return display->platform.battlemage;
case INTEL_DISPLAY_WA_14025769978:
return DISPLAY_VER(display) == 35;
default:
drm_WARN(display->drm, 1, "Missing Wa number: %s\n", name);
break;

1
drivers/gpu/drm/i915/display/intel_display_wa.h
View File

@ -27,6 +27,7 @@ enum intel_display_wa {
INTEL_DISPLAY_WA_14011503117,
INTEL_DISPLAY_WA_22014263786,
INTEL_DISPLAY_WA_15018326506,
INTEL_DISPLAY_WA_14025769978,
};
bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name);

10
drivers/gpu/drm/i915/display/intel_fbc.c
View File

@ -964,8 +964,14 @@ static void fbc_sys_cache_update_config(struct intel_display *display, u32 reg,
lockdep_assert_held(&display->fbc.sys_cache.lock);
/* Cache read enable is set by default */
reg |= FBC_SYS_CACHE_READ_ENABLE;
/*
* Wa_14025769978:
* Fixes: SoC hardware issue in read caching
* Workaround: disable cache read setting which is enabled by default.
*/
if (!intel_display_wa(display, 14025769978))
/* Cache read enable is set by default */
reg |= FBC_SYS_CACHE_READ_ENABLE;
intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG, reg);