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PCI: Allow D3 for native hotplug-capable Root Ports on non-x86 platforms

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Commit eb3b5bf1a8 ("PCI: Whitelist native hotplug ports for runtime D3"),
prevented native hotplug-capable Root Ports from entering D3 citing issues
on old Intel SkyLake Xeon-SP platform.

But there is no reason to restrict D3 for native hotplug-capable Root Ports
on non-x86 platforms. We recently enabled D3 on non hotplug-capable Root
Ports on non-x86 platforms (specifically for DT platforms) in commit
a5fb3ff632 ("PCI: Allow PCI bridges to go to D3Hot on all non-x86"). So
do the same for native hotplug-capable Root Ports as well.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260729165005.896725-1-manivannan.sadhasivam@oss.qualcomm.com
This commit is contained in:
Manivannan Sadhasivam 2026-07-29 18:50:05 +02:00 committed by Bjorn Helgaas
parent dc59e4fea9
commit d4c79b63d8
1 changed files with 4 additions and 4 deletions
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8
drivers/pci/pci.c
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@ -3020,11 +3020,11 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge)
return true;
/*
* Hotplug ports handled natively by the OS were not validated
* by vendors for runtime D3 at least until 2018 because there
* was no OS support.
* Hotplug ports handled natively by the OS on x86 platforms
* were not validated by vendors for runtime D3 at least until
* 2018 because there was no OS support.
*/
if (bridge->is_pciehp)
if (IS_ENABLED(CONFIG_X86) && bridge->is_pciehp)
return false;
if (dmi_check_system(bridge_d3_blacklist))