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MMC host:

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- rtsx_pci_sdmmc: Fix signal voltage switch
  - sdhci-of-dwcmshc: A couple of fixes for Eswin EIC7700
  - sdhci-of-dwcmshc: Fix support for HS200/HS400 mode
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Merge tag 'mmc-v6.19-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

Pull MMC fixes from Ulf Hansson:

 - rtsx_pci_sdmmc: Fix signal voltage switch

 - sdhci-of-dwcmshc:
     - A couple of fixes for Eswin EIC7700
     - Fix support for HS200/HS400 mode

* tag 'mmc-v6.19-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
  mmc: sdhci-of-dwcmshc: Fix DMA 128MB boundary for Eswin EIC7700
  mmc: sdhci-of-dwcmshc: Fix init for AXI clock for Eswin EIC7700
  mmc: rtsx_pci_sdmmc: implement sdmmc_card_busy function
  mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode
This commit is contained in:
Linus Torvalds 2026-01-23 13:01:28 -08:00
commit d4be90cce6
2 changed files with 55 additions and 0 deletions
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41
drivers/mmc/host/rtsx_pci_sdmmc.c
View File

@ -1306,6 +1306,46 @@ static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
return err;
}
static int sdmmc_card_busy(struct mmc_host *mmc)
{
struct realtek_pci_sdmmc *host = mmc_priv(mmc);
struct rtsx_pcr *pcr = host->pcr;
int err;
u8 stat;
u8 mask = SD_DAT3_STATUS | SD_DAT2_STATUS | SD_DAT1_STATUS
| SD_DAT0_STATUS;
mutex_lock(&pcr->pcr_mutex);
rtsx_pci_start_run(pcr);
err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
SD_CLK_TOGGLE_EN);
if (err)
goto out;
mdelay(1);
err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
if (err)
goto out;
err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
out:
mutex_unlock(&pcr->pcr_mutex);
if (err)
return err;
/* check if any pin between dat[0:3] is low */
if ((stat & mask) != mask)
return 1;
else
return 0;
}
static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
{
struct realtek_pci_sdmmc *host = mmc_priv(mmc);
@ -1418,6 +1458,7 @@ static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
.get_ro = sdmmc_get_ro,
.get_cd = sdmmc_get_cd,
.start_signal_voltage_switch = sdmmc_switch_voltage,
.card_busy = sdmmc_card_busy,
.execute_tuning = sdmmc_execute_tuning,
.init_sd_express = sdmmc_init_sd_express,
};

14
drivers/mmc/host/sdhci-of-dwcmshc.c
View File

@ -739,6 +739,13 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock
sdhci_writel(host, extra, reg);
if (clock <= 52000000) {
if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
dev_err(mmc_dev(host->mmc),
"Can't reduce the clock below 52MHz in HS200/HS400 mode");
return;
}
/*
* Disable DLL and reset both of sample and drive clock.
* The bypass bit and start bit need to be set if DLL is not locked.
@ -1588,6 +1595,7 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm
{
u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
unsigned int val, hsp_int_status, hsp_pwr_ctrl;
static const char * const clk_ids[] = {"axi"};
struct of_phandle_args args;
struct eic7700_priv *priv;
struct regmap *hsp_regmap;
@ -1605,6 +1613,11 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm
return ret;
}
ret = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv,
ARRAY_SIZE(clk_ids), clk_ids);
if (ret)
return ret;
ret = of_parse_phandle_with_fixed_args(dev->of_node, "eswin,hsp-sp-csr", 2, 0, &args);
if (ret) {
dev_err(dev, "Fail to parse 'eswin,hsp-sp-csr' phandle (%d)\n", ret);
@ -1726,6 +1739,7 @@ static const struct sdhci_ops sdhci_dwcmshc_eic7700_ops = {
.set_uhs_signaling = sdhci_eic7700_set_uhs_wrapper,
.set_power = sdhci_set_power_and_bus_voltage,
.irq = dwcmshc_cqe_irq_handler,
.adma_write_desc = dwcmshc_adma_write_desc,
.platform_execute_tuning = sdhci_eic7700_executing_tuning,
};