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arm64: errata: Add NXP i.MX8QM/8QP workaround for A53 cache coherency issue
According to NXP errata document IMX8_1N94W[1], the i.MX8QuadMax and
i.MX8QuadPlus SoCs suffer from a cache coherency issue (ERR050104). The
upper bits, above bit 35, of the ARADDR and ACADDR buses within the Arm
A53 subsystem have been incorrectly connected. This causes some TLBI and
IC maintenance operations exchanged between the A53 and A72 core
clusters to be corrupted.
The workaround requires:
- Downgrading targeted TLBI operations to broadcast-all variants.
Instead of patching the low-level __TLBI_1 macro (which causes
excessive over-invalidation), redirect high-level TLB flush
functions (flush_tlb_mm, __do_flush_tlb_range,
flush_tlb_kernel_range, __flush_tlb_kernel_pgtable) to use VMALLE1IS
via alternatives.
- Upgrading IC IVAU to IC IALLUIS for both kernel (via ALTERNATIVE in
invalidate_icache_by_line) and EL0 userspace (via trap-and-upgrade
in user_cache_maint_handler with SCTLR_EL1.UCI=0).
- Disabling KVM since correct TLB maintenance cannot be guaranteed
for guests.
- No need to touch SMMU Broadcast TLB Maintenance (BTM) since the
arm-smmu driver does not use it.
SoC detection uses devicetree compatible string "fsl,imx8qm" or
"fsl,imx8qp" since the boot CPU MIDR_EL1 (0x410fd034) and AIDR_EL1 (0)
are not unique to these SoCs.
[1] https://www.nxp.com/docs/en/errata/IMX8_1N94W.pdf
[ Reworked per review feedback from Will Deacon and Mark Rutland:
- Move TLBI workaround from __TLBI_1 macro to high-level flush
functions to avoid excessive over-invalidation
- Add kernel IC IVAU upgrade via ALTERNATIVE in assembler.h
- Add cpucap_is_possible() entry for compile-time elimination]
Tested-by: Franz Schnyder <franz.schnyder@toradex.com> # Toradex Apalis iMX8QM
Co-developed-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
[catalin.marinas@arm.com: Kconfig and errata text, sysreg_clear_set(), of_machine_compatible_match()]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Peng Fan
Catalin Marinas
parent
cea68e7489
commit
d44e08dab2
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@ -327,6 +327,8 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Freescale/NXP | i.MX 8QM/8QP | ERR050104 | NXP_IMX8QM_ERRATUM_ERR050104|
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
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+----------------+-----------------+-----------------+-----------------------------+
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@ -1455,6 +1455,28 @@ config ROCKCHIP_ERRATUM_3588001
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If unsure, say Y.
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config NXP_IMX8QM_ERRATUM_ERR050104
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bool "NXP iMX8QM/QP ERR050104: broken cache/TLB invalidation broadcast"
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default y
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help
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On iMX8QM (QuadMax) and iMX8QP (QuadPlus), address bits above bit 35
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in the A53 subsystem ARADDR and ACADDR buses are incorrectly
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connected. This corrupts targeted TLBI and IC broadcasts exchanged
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between the A53 and A72 core clusters.
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Work around this by redirecting targeted TLBI operations to
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broadcast-all variants (VMALLE1IS) in the high-level TLB flush
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functions, upgrading IC IVAU to IC IALLUIS for both kernel and
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user-space, and disabling KVM since correct TLB maintenance
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cannot be guaranteed for guests.
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The user-space IC IVAU is upgraded by trapping it to the kernel
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(SCTLR_EL1.UCI cleared). This also traps the user DC CVAU, DC CVAC,
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DC CVAP, DC CVADP and DC CIVAC instructions, making user cache
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maintenance slower on the affected SoCs.
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If unsure, say Y.
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config SOCIONEXT_SYNQUACER_PREITS
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bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
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default y
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@ -451,6 +451,10 @@ alternative_else_nop_endif
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* Corrupts: tmp1, tmp2
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*/
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.macro invalidate_icache_by_line start, end, tmp1, tmp2, fixup
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alternative_if ARM64_WORKAROUND_NXP_ERR050104
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ic ialluis
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b .Licache_done\@
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alternative_else_nop_endif
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icache_line_size \tmp1, \tmp2
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sub \tmp2, \tmp1, #1
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bic \tmp2, \start, \tmp2
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@ -459,6 +463,7 @@ alternative_else_nop_endif
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add \tmp2, \tmp2, \tmp1
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cmp \tmp2, \end
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b.lo .Licache_op\@
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.Licache_done\@:
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dsb ish
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isb
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@ -66,6 +66,8 @@ cpucap_is_possible(const unsigned int cap)
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return IS_ENABLED(CONFIG_ARM64_ERRATUM_3194386);
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case ARM64_WORKAROUND_4193714:
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return IS_ENABLED(CONFIG_ARM64_ERRATUM_4193714);
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case ARM64_WORKAROUND_NXP_ERR050104:
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return IS_ENABLED(CONFIG_NXP_IMX8QM_ERRATUM_ERR050104);
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case ARM64_MPAM:
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/*
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* KVM MPAM support doesn't rely on the host kernel supporting MPAM.
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@ -73,8 +73,10 @@ enum kvm_mode {
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};
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#ifdef CONFIG_KVM
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enum kvm_mode kvm_get_mode(void);
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void kvm_force_disabled(void);
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#else
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static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; };
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static inline void kvm_force_disabled(void) { };
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#endif
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extern unsigned int __ro_after_init kvm_sve_max_vl;
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@ -378,9 +378,13 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
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unsigned long asid;
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dsb(ishst);
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asid = __TLBI_VADDR(0, ASID(mm));
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__tlbi(aside1is, asid);
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__tlbi_user(aside1is, asid);
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if (alternative_has_cap_unlikely(ARM64_WORKAROUND_NXP_ERR050104)) {
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__tlbi(vmalle1is);
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} else {
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asid = __TLBI_VADDR(0, ASID(mm));
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__tlbi(aside1is, asid);
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__tlbi_user(aside1is, asid);
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}
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__tlbi_sync_s1ish(mm);
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mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL);
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}
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@ -580,23 +584,28 @@ static __always_inline void __do_flush_tlb_range(struct vm_area_struct *vma,
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asid = ASID(mm);
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switch (flags & (TLBF_NOWALKCACHE | TLBF_NOBROADCAST)) {
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case TLBF_NONE:
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__flush_s1_tlb_range_op(vae1is, start, pages, stride,
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asid, tlb_level);
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break;
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case TLBF_NOWALKCACHE:
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__flush_s1_tlb_range_op(vale1is, start, pages, stride,
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asid, tlb_level);
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break;
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case TLBF_NOBROADCAST:
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/* Combination unused */
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BUG();
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break;
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case TLBF_NOWALKCACHE | TLBF_NOBROADCAST:
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__flush_s1_tlb_range_op(vale1, start, pages, stride,
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asid, tlb_level);
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break;
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if (alternative_has_cap_unlikely(ARM64_WORKAROUND_NXP_ERR050104) &&
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!(flags & TLBF_NOBROADCAST)) {
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__tlbi(vmalle1is);
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} else {
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switch (flags & (TLBF_NOWALKCACHE | TLBF_NOBROADCAST)) {
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case TLBF_NONE:
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__flush_s1_tlb_range_op(vae1is, start, pages, stride,
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asid, tlb_level);
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break;
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case TLBF_NOWALKCACHE:
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__flush_s1_tlb_range_op(vale1is, start, pages, stride,
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asid, tlb_level);
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break;
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case TLBF_NOBROADCAST:
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/* Combination unused */
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BUG();
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break;
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case TLBF_NOWALKCACHE | TLBF_NOBROADCAST:
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__flush_s1_tlb_range_op(vale1, start, pages, stride,
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asid, tlb_level);
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break;
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}
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}
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if (!(flags & TLBF_NONOTIFY))
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@ -657,7 +666,8 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end
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end = round_up(end, stride);
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pages = (end - start) >> PAGE_SHIFT;
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if (__flush_tlb_range_limit_excess(pages, stride)) {
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if (alternative_has_cap_unlikely(ARM64_WORKAROUND_NXP_ERR050104) ||
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__flush_tlb_range_limit_excess(pages, stride)) {
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flush_tlb_all();
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return;
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}
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@ -675,10 +685,14 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end
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*/
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static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr)
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{
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unsigned long addr = __TLBI_VADDR(kaddr, 0);
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dsb(ishst);
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__tlbi(vaae1is, addr);
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if (alternative_has_cap_unlikely(ARM64_WORKAROUND_NXP_ERR050104)) {
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__tlbi(vmalle1is);
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} else {
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unsigned long addr = __TLBI_VADDR(kaddr, 0);
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__tlbi(vaae1is, addr);
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}
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__tlbi_sync_s1ish_kernel();
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isb();
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}
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@ -6,6 +6,7 @@
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*/
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#include <linux/arm-smccc.h>
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#include <linux/of.h>
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#include <linux/types.h>
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#include <linux/cpu.h>
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#include <asm/cpu.h>
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@ -13,6 +14,7 @@
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#include <asm/cpufeature.h>
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#include <asm/fpsimd.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_host.h>
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#include <asm/smp_plat.h>
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static u64 target_impl_cpu_num;
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@ -200,6 +202,33 @@ cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
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sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
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}
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#ifdef CONFIG_NXP_IMX8QM_ERRATUM_ERR050104
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static bool
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is_imx8qm_soc(const struct arm64_cpu_capabilities *entry, int scope)
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{
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static const char * const compats[] = {
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"fsl,imx8qm",
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"fsl,imx8qp",
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NULL
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};
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return of_machine_compatible_match(compats);
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}
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static void
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cpu_enable_imx8qm_err050104(const struct arm64_cpu_capabilities *__unused)
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{
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/* Trap the EL0 IC IVAU so that it can be upgraded to IC IALLUIS */
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sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
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/*
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* TLB maintenance cannot be guaranteed correct for guests, so
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* disable KVM as if kvm-arm.mode=none was passed on the command line.
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*/
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kvm_force_disabled();
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}
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#endif
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#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
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.matches = is_affected_midr_range, \
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.midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
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@ -1030,6 +1059,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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.type = ARM64_CPUCAP_SYSTEM_FEATURE,
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.matches = has_broken_gic_v3_seis,
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},
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#ifdef CONFIG_NXP_IMX8QM_ERRATUM_ERR050104
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{
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.desc = "NXP erratum ERR050104",
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.capability = ARM64_WORKAROUND_NXP_ERR050104,
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.type = ARM64_CPUCAP_SOC_ERRATUM,
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.matches = is_imx8qm_soc,
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.cpu_enable = cpu_enable_imx8qm_err050104,
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},
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#endif
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{
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}
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};
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@ -586,6 +586,8 @@ static void user_cache_maint_handler(unsigned long esr, struct pt_regs *regs)
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break;
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case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */
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__user_cache_maint("ic ivau", address, ret);
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if (cpus_have_final_cap(ARM64_WORKAROUND_NXP_ERR050104) && !ret)
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asm volatile("ic ialluis");
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break;
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default:
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force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
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@ -3159,6 +3159,11 @@ static int __init early_kvm_mode_cfg(char *arg)
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}
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early_param("kvm-arm.mode", early_kvm_mode_cfg);
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void kvm_force_disabled(void)
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{
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kvm_mode = KVM_MODE_NONE;
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}
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static int __init early_kvm_wfx_trap_policy_cfg(char *arg, enum kvm_wfx_trap_policy *p)
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{
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if (!arg)
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@ -125,6 +125,7 @@ WORKAROUND_DEVICE_LOAD_ACQUIRE
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WORKAROUND_DISABLE_CNP
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WORKAROUND_GICv3_BROKEN_SEIS
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WORKAROUND_NVIDIA_OLYMPUS_1027
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WORKAROUND_NXP_ERR050104
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WORKAROUND_PMUV3_IMPDEF_TRAPS
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WORKAROUND_QCOM_FALKOR_E1003
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WORKAROUND_QCOM_ORYON_CNTVOFF
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